Gregory M. Fritz

Resistivity of copper interconnects beyond the 7 nm node

The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.

Subtractive W contact and local interconnect co-integration (CLIC)

The resistivity of W interconnects deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD) is studied. The impacts of the deposition process and liner film stacks are explored. The results show acceptable resistivity for local interconnect (LI) applications with a linewidth down to 20nm and a wiring pitch down to 60nm. An integration scheme for combining a CVD W contact and local interconnect is explored as a means of providing a compact wiring solution with minimal impact on process complexity. The wiring concept is validated by integrating the local interconnects with trigate transistors.