Guanping Wu

Design and Fabrication of Dual-Trench Epitaxial Diode Array for High-Density Phase-Change Memory

For the first time, the design and fabrication of dual-trench epitaxial p/n junction diodes in a commercially standard 0.13-μm complementary metal-oxide-semiconductor process are introduced in this letter. The 16 × 16 diode arrays with 0.196-μm2 (5F2) cell size have been successfully fabricated, showing the excellent electrical properties of its sufficient current drive ability in excess of 12.5 mA/μm2, large on-/off-current ratio greater than nine orders of magnitude, and its excellent crosstalk immunity. A dual-trench epitaxial diode could be used as the access device for high-density phase-change memory and could also produce highly scalable embedded applications for 45-nm node and beyond, due to its unique process integration scheme.

An 8-Mb Phase-Change Random Access Memory Chip Based on a Resistor-on-Via-Stacked-Plug Storage Cell

In this letter, an 8-Mb phase-change random access memory (PCRAM) chip has been developed in a 130-nm 4-ML standard CMOS technology based on a Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase-change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2-V nMOS device. The currents of the set and reset operations are 0.4 and 2.2 mA, respectively. The best endurance is over 1010 cycles.

Optimization of 40-nm Node Epitaxial Diode Array for Phase-Change Memory Application

A numerical model of an epitaxial (EPI) diode array for next-generation memory device application, including phase-change memory, has been presented. According to a diode array process scheme and technology computer-aided design (TCAD) simulation results, a quasi-physical model with a buried n+ layer dosage, EPI layer thickness, and breakdown voltage (BVD) correlation is proposed to improve electrical performance. From the optimal silicon-based results, a 16×16 diode array shows a drive current density of ~56.6 mA/μm2, a BVD of ~8 V, a Jon/Joff ratio of ~109, and crosstalk immunity. Additionally, this calibrated physical model can be applied in the next generation of silicon-based fabrication with parameters extraction.

Cost-Effective Schottky-Barrier Diode Array With Ni–Silicidation Accessing Low Power Phase-Change Memory

A cost-effective fabrication of Schottky-barrier (SB) diode steering element for low power phase-change memory (PCM) application is realized. While superior drivability in conventional PN diode array, SB diode array with 0.0193- μm2 (5F2), performing higher switching speed, sufficient drive current density of ~ 26.30 mA/μm2, disturbance immunity, and lower power consumption has been manufactured under 40-nm standard complementary metal oxide semiconductor technology. Simultaneously, different performance specifications, including integration scheme, JON/JOFF ratio, temperature characteristics, and scalability have been studied in detail and compared in two categories of accessing diode arrays. It manifests that the scaled SB diode array is suitable for full operation of PCM.

Optimization of Anomalous Cells with High SET Resistance in Phase Change Memory Arrays

The resistance distribution in the crystalline (SET) state of phase change memory (PCM) is experimentally investigated at the array level using an 8 Mbit test chip. The SET distribution shows a high resistance tail, which potentially affects the reading margin of the chip. To further understand the anomalous behaviors of these tail cells, the SET resistances are characterized in terms of the programming pulse current magnitude and duration. These tail cells are probably caused by incomplete crystallization of the inactive region of phase change material. Finally, an optimization approach of applying a direct current of 0.6 mA to these tail cells is proposed and experimentally verified.

Study and Improvement on Tungsten Plug Corrosion in CMP Process for PCRAM

To reduce the reset current for developing reliable high density phase change random access memory (PCRAM), small bottom electrode contact (BEC) size formation is a critical process. One of the failure mode for the process is the corrosion of tungsten plug, which is caused by tungsten chemical mechanical planarization (CMP) process. In this paper, this CMP process was analyzed. The tungsten polishing step process was characterized by the coefficient j and it shows good performance in tungsten polishing process. The alkali and acidic buff slurry effect on tungsten plug performance were studied. The result shows that the recess free tungsten plug had been fabricated with acidic buff slurry. The electric results confirm that it can fulfill the set operation of PCRAM cells.

Temperature and series resistance effect on electrical characteristics of epitaxial diode array for phase-change memory application

Temperature dependence and series resistance effect on the electrical characteristics of 40nm node epitaxial PN junction diode array for phase-change memory application were investigated in a temperature range of 233K-358K. According to dual-trench isolation and silicon epitaxial diode array process scheme, buried N+ layer (BNL) acting as word line has played a significant role of phase-change memory structure design and access device scaling. The current-voltage (I-V) curve of the PN junction shows correlation with size dependence and temperature variation. By extrapolating the forward saturation current, the evaluated ideality factor was observed to decrease from 1.18 to 1.06 in the temperature range from 233 to 358K. With 16×16 diode array dimension scaling and BNL series resistance shrinking, forward current of PN junction in predominant role increases with temperature. Temperature and size dependence analysis can assist device design to promote 16×16 epitaxial diode array electrical characteristics for next-generation non-volatile memory application, especially for phase-change memory.

Chemical mechanical planarization of amorphous Ge2Sb2Te5 with a soft pad

Chemical mechanical planarization (CMP) of amorphous Ge2Sb2Te5 (a-GST) is investigated using two typical soft pads (politex REG and AT) in acidic slurry. After CMP, it is found that the removal rate (RR) of a-GST increases with an increase of runs number for both pads. However, it achieves the higher RR and better surface quality of a-GST for an AT pad. The in-situ sheet resistance (Rs) measure shows the higher Rs of a-GST polishing can be gained after CMP using both pads and the high Rs is beneficial to lower the reset current for the PCM cells. In order to find the root cause of the different RR of a-GST polishing with different pads, the surface morphology and characteristics of both new and used pads are analyzed, it shows that the AT pad has smaller porosity size and more pore counts than that of the REG pad, and thus the AT pad can transport more fresh slurry to the reaction interface between the pad and a-GST, which results in the high RR of a-GST due to enhanced chemical reaction.

Analysis of anomalous cells within RESET distribution for phase change memory

Resistance distributions of the crystalline (SET) state and amorphous (RESET) state for phase change memory (PCM) are experimentally investigated at the array level. The RESET distribution shows a low resistance tail, which potentially affects the reading margin of the chip. These tail cells are divided into two types by resistance programming current (R-IP) and current voltage (I-V) characteristics. Finally, approaches of improving the integration process to remove the Type-1 tail cells and optimizing the programming operation to repair the Type-2 tail cells are proposed.

A comparison of the Ge-Sb-Te and Si-Sb-Te film oxidization at atmosphere

New phase change materials development has become one of the most critical modules in the fabrication of low power consumption and good data retention phase change memory (PCM). Among various candidates of new phase change materials, SiSbTe (SST) is one of the most promising materials due to its benefits of low RESET current, high crystallization temperature, good adhesion and small volume shrinkage during phase change from amorphous to crystalline state. However, the oxidization of SST film was found when exposing to the atmosphere. By analyzing the depth profile of chemical states, we found oxygen more easily penetrated into the SST film and bonded with Si and Sb compared to GeSbTe (GST) film. The oxidization mechanism between SST and GST was briefly discussed. We achieved 80% improvement of oxidization issue by nitrogen and argon surface treatment. We proposed a manufacturing solution of SST for PCM.