Zuoya Yang

Design and Fabrication of Dual-Trench Epitaxial Diode Array for High-Density Phase-Change Memory

For the first time, the design and fabrication of dual-trench epitaxial p/n junction diodes in a commercially standard 0.13-μm complementary metal-oxide-semiconductor process are introduced in this letter. The 16 × 16 diode arrays with 0.196-μm2 (5F2) cell size have been successfully fabricated, showing the excellent electrical properties of its sufficient current drive ability in excess of 12.5 mA/μm2, large on-/off-current ratio greater than nine orders of magnitude, and its excellent crosstalk immunity. A dual-trench epitaxial diode could be used as the access device for high-density phase-change memory and could also produce highly scalable embedded applications for 45-nm node and beyond, due to its unique process integration scheme.

Cost-Effective Schottky-Barrier Diode Array With Ni–Silicidation Accessing Low Power Phase-Change Memory

A cost-effective fabrication of Schottky-barrier (SB) diode steering element for low power phase-change memory (PCM) application is realized. While superior drivability in conventional PN diode array, SB diode array with 0.0193- μm2 (5F2), performing higher switching speed, sufficient drive current density of ~ 26.30 mA/μm2, disturbance immunity, and lower power consumption has been manufactured under 40-nm standard complementary metal oxide semiconductor technology. Simultaneously, different performance specifications, including integration scheme, JON/JOFF ratio, temperature characteristics, and scalability have been studied in detail and compared in two categories of accessing diode arrays. It manifests that the scaled SB diode array is suitable for full operation of PCM.

Optimization of Anomalous Cells with High SET Resistance in Phase Change Memory Arrays

The resistance distribution in the crystalline (SET) state of phase change memory (PCM) is experimentally investigated at the array level using an 8 Mbit test chip. The SET distribution shows a high resistance tail, which potentially affects the reading margin of the chip. To further understand the anomalous behaviors of these tail cells, the SET resistances are characterized in terms of the programming pulse current magnitude and duration. These tail cells are probably caused by incomplete crystallization of the inactive region of phase change material. Finally, an optimization approach of applying a direct current of 0.6 mA to these tail cells is proposed and experimentally verified.

Analysis of anomalous cells within RESET distribution for phase change memory

Resistance distributions of the crystalline (SET) state and amorphous (RESET) state for phase change memory (PCM) are experimentally investigated at the array level. The RESET distribution shows a low resistance tail, which potentially affects the reading margin of the chip. These tail cells are divided into two types by resistance programming current (R-IP) and current voltage (I-V) characteristics. Finally, approaches of improving the integration process to remove the Type-1 tail cells and optimizing the programming operation to repair the Type-2 tail cells are proposed.

Optical emission spectroscopy analysis for Ge2Sb2Te5 etching endpoint detection in HBr/He plasma

In the fabrication of phase change memory devices, HBr/He gas is employed in patterning Ge2Sb2Te5 (GST) because it is damage free to GST sidewall. Accurate and reproducible endpoint detection methods are necessary in this etching process. In-situ optical emission spectroscopy (OES) is collected and analyzed to control the GST etching process due to its non-invasiveness. By analyzing the light emitted from plasma, we report an effective etch endpoint detection method for GST etching process is developed and the results are also confirmed using scanning electron micrographs.

16kb Phase Change Memory Test Chip with 0.18-μm Process

A 16kb phase change memory with standard CMOS 0.18-μm test chip has been demonstrated. The critical integration technology of the phase change material fabrication and the standard CMOS process has been improved. Full integration of PCRAM, including memory cell, array structure, critical circuit module, and physical layout, has been designed and verified. Test results about PCM cell and circuit module has been generated.