Guido Montorsi

Design of parallel concatenated convolutional codes

A parallel concatenated convolutional coding scheme consists of two constituent systematic: convolutional encoders linked by an interleaver. The information bits at the input of the first encoder are scrambled by the interleaver before entering the second encoder. The codewords of the parallel concatenated code consist of the information bits followed by the parity check bits of both encoders. Parallel concatenated codes (turbo codes), decoded through an iterative decoding algorithm of relatively low complexity, have been shown to yield remarkable coding gains close to theoretical limits. We characterize the separate contributions that the interleaver length and constituent codes give to the overall performance of the parallel concatenated code, and present some guidelines for the optimal design of the constituent convolutional codes.

Parallel concatenated trellis coded modulation

In this paper, we propose a new solution to parallel concatenation of trellis codes with multilevel amplitude/phase modulations and a suitable bit by bit iterative decoding structure. Examples are given for throughput 2 and 4 bits/sec/Hz with 8 PSK, 16 QAM, and 64 QAM modulations. For parallel concatenated trellis codes in the examples, rate 2/3 and 4/5, 8, and 16-state binary convolutional codes with Ungerboeck mapping by set partitioning (natural mapping), a reordered mapping, and Gray code mapping are used. The performance of these codes is within 1 dB from the Shannon limit at a bit error probability of 10/sup -7/ for a given throughput, which outperforms the performance of all codes reported in the past for the same throughput.

Soft-Input Soft-Output Modules for the Construction and Distributed Iterative Decoding of Code Networks

Soft-input soft-output building blocks (modules) are presented to construct and iteratively decode in a distributed fashion code networks, a new concept that includes, and generalizes, various forms of concatenated coding schemes. Among the modules, a central role is played by the SISO module (and the underlying algorithm): it consists of a four-port device performing a processing of the sequences of two input probability distributions by constraining them to the code trellis structure. The SISO and other soft-input soft-output modules are employed to construct and decode a variety of code networks, including “turbo codes” and serially concatenated codes with interleavers.

Mapping interleaving laws to parallel turbo and LDPC decoder architectures

For high-data-rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process from/into the memory. This consideration applies to the two main classes of turbo-like codes, i.e., turbo codes and low-density parity-check (LDPC) codes. Contrary to the literature belief, we prove in this paper that there is no need for an ad hoc code design to meet the parallelism requirement, because, for any code and any choice of the scheduling of the reading/writing operations, there is a suitable mapping of the variables in the memory that grants a collision-free access. The proof is constructive, i.e., it gives an algorithm that obtains the desired collision-free mapping. The algorithm is applied to two simple examples, one for turbo codes and one for LDPC codes, to illustrate how the algorithm works.

Design of fixed-point iterative decoders for concatenated codes with interleavers

We discuss the effects of quantization on the performance of the iterative decoding algorithm of concatenated codes with interleavers. Quantization refers here to the log-likelihood ratios coming from the soft demodulator and to the extrinsic information passed from one stage of the decoder to the next. We discuss the cases of a single soft-input soft-output (SISO) module, in its additive log-likelihood version (L-SISO), performing sequentially all iterations (an implementation solution coping with medium-low data rate as compared with the hardware clock), and that of a pipelined structure in which a dedicated hardware is in charge of each SISO operation (an implementation suitable for high data rates). We give design rules in both cases, and show that a suitable rescaling of the extrinsic information yields almost ideal performance with the same number of bits (five) representing both log-likelihood ratios and extrinsic information at any decoder stage.

Soft-output decoding algorithms for continuous decoding of parallel concatenated convolutional codes

We propose new decoding algorithms to be embedded in the iterative decoding strategy of parallel concatenated convolutional codes. They are derived from the optimum maximum-a-posteriori algorithm and permit a continuous decoding of the coded sequence without requiring trellis termination of the constituent codes. Two basic versions of the continuous algorithm and their suboptimum simplifications are described. Simulation results refer to the applications of the new algorithms to a highly efficient rate 1/3 concatenated code; they show performance only 0.6 dB worse than the Shannon limit.

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues

This tutorial paper gives an overview of the implementation aspects related to turbo decoders, where the term turbo generally refers to iterative decoders intended for parallel concatenated convolutional codes as well as for serial concatenated convolutional codes. We start by considering the general structure of iterative decoders and the main features of the soft-input soft-output algorithm that forms the heart of iterative decoders. Then, we show that very efficient parallel architectures are available for all types of turbo decoders allowing high-speed implementations. Other implementation aspects like quantization issues and stopping rules used in conjunction with buffering for increasing throughput are considered. Finally, we perform an evaluation of the complexities of the turbo decoders as a function of the main parameters of the code.

MHOMS: high-speed ACM modem for satellite applications

This article presents the novel FPGA-based 1 Gb/s near-Shannon-limit ACM modem developed within the MHOMS program with particular focus on the advanced modem algorithm solutions devised. A number of powerful FEC schemes have been analyzed as possible candidates for the MHOMS modem, and the final selection is justified in terms of the best tradeoff between complexity and performance. State-of-the-art modulation and demodulation algorithms are also presented, including nonlinearity dynamic precompensation techniques and innovative synchronization strategies required by the selected powerful modulation and coding schemes. Overall modem performances are also shown for a variety of spectral efficiencies.

Performance evaluation of trellis-coded modulation schemes

A description of the algorithms to evaluate the main parameters determining the performance of a trellis-coded modulation (TCM) scheme is presented. TCM schemes are divided into classes that have an increasing degree of symmetry, so as to properly match the various algorithms to each class. The algorithms are compared in terms of computational complexity and tested on a set of multidimensional PSK codes. >

A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code

This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-/spl mu/m CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone).