Guilherme Lujan

On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

The work function of ALD TiN was found to be above 5 eV after RTP annealing below 800/spl deg/C in a nitrogen atmosphere, while higher annealing temperatures cause a drop in work function by about 0.3-0.5 eV. The effect was found for TiN metal gates on both SiO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics in MOS-capacitors and was seen in C-V as well as in I-V measurements. On the contrary, annealing of SiO/sub 2/ capacitors in oxygen-enriched N/sub 2/ atmosphere increased the work function. A variation in EOT of less than 2 A was demonstrated for the various annealing temperatures, concluding that the ALD TiN is stable in contact with the different dielectric materials. However, the decrease in work function that is found in this investigation may implicate that ALD TiN is less suitable as a metal gate for pMOSFETs.

Electrical characterisation of high-k materials prepared by atomic layer CVD

The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO/sub 2/ as the gate dielectric. Replacement of SiO/sub 2/ with a high dielectric constant material allows an increase in the physical oxide thickness, while maintaining a low equivalent oxide thickness (EOT) and low direct tunnelling current. The high-k gate dielectric of choice will most likely be a deposited film, which makes the replacement of SiO/sub 2/, a thermally grown layer, even more challenging. Atomic layer CVD (ALCVD/sup TM/) is a well-controlled surface saturating process using gas-solid interactions to deposit thin films. The technique results in covalent bonding between the gaseous precursors and the surface bonding sites. ALCVD/sup TM/ provides highly uniform layers and the possibility to deposit many materials, including mixed oxide layers and nano-laminates. Some of the challenges facing high-k materials include achieving a high quality Si/high-k interface, film stability and solving reliability and integration issues. In this paper, we use MOS capacitors to investigate these challenges for Al/sub 2/O/sub 3/-TiN and Al/sub 2/O/sub 3/-ZrO/sub 2/-TiN gate stacks.

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors

Abstract Direct-etched HfO2/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO2/poly transistors. The performance enhancement requires a combination of EOT scaling and an appropriate interface layer control. The performance of the direct-etched TaN gated HfO2 based transistors is also compared to the performance of similar TaN gated SiON based transistors. It is observed that for equal gm the leakage is lower for HfO2 based transistors, despite the lower EOT for the HfO2 based devices.

Modelling mobility degradation due to remote coulomb scattering from dielectric charges and its impact on MOS device performance

The electron mobility in high-k transistors is degraded when compared to silicon oxide transistors. So far this problem has hampered the production of high-k transistors. One of the main causes of the low mobility is remote Coulomb scattering from charges in the dielectric. In this paper we analyse how the dielectric constants can change the mobility in a high-k stacked transistors. When an interface layer (IL) is used between the semiconductor and the high-k dielectric, the increase of the dielectric constant of the IL degrades the mobility. When the dielectric constant of the high-k layer is increased, the mobility is increased. These two opposite effects can be explained by an increase of the electric coupling in the first case and by an increase of the fringing field in the second. We study the electron mobility as a function of dielectric constant and thickness for three different stacks. Higher permittivity layers in combination with an interface layer free of charges are desirable to improve mobility.

Impact of ALCVD and PVD Titanium Nitride Deposition on Metal Gate Capacitors

In this paper it will be shown that the deposition method is an important parameter for the electrical properties of the metal gate. Indeed, ALCVD(Atomic Layer Chemical Vapor Deposition) TiN metal has a 5.3eV workfunction, suitable for PMOS devices. The PVD sputtered (Physical Vapor Deposition) TiN has a lower workfunction around 4.8eV and is mid-gap like. The PVD TiN capacitors have a higher effective oxide charge than the ALCVD capacitors as extracted from capacitance measurements and from workfunction calculations. PVD TiN also exhibits process-induced damage as seen from leakage measurements.

Mobility degradation in high-k transistors: the role of the charge scattering

In this paper, we propose a model to calculate the mobility degradation due to remote Coulomb scattering. The model is able to predict the effects of an arbitrary charge distribution in the gate dielectric. We model the mobility degradation for HfO/sub 2/ transistors. An exponential charge distribution results in the best agreement. We observe also that the inversion charge is able to screen the effect of the remote charge, thus increasing the mobility while decreasing the EOT.

Experimental analysis of a Ge-HfO/sub 2/-TaN gate stack with a large amount of interface states

First, the quality of the Ge-HfO/sub 2/ interface of early MOS capacitors is studied. The characterization difficulties related to the introduction of germanium as substrate material are analyzed and can be subdivided in problems due to the initial low quality of the samples, and due to the different material properties as compared to silicon. It is concluded from measurements of CV-curves at low temperature, gated diodes, and conductance analysis, that a large number interface states prevents inversion for p-substrate capacitors and accumulation for n-substrate capacitors. The paper then briefly discusses the difficulties related to the characterization of early MOS transistors on germanium substrates. These difficulties are mainly caused by a large amount of junction leakage.

Investigation of poly-Si/HfO/sub 2/ gate stacks in a self-aligned 70nm MOS process flow

NMOS and PMOS transistors with poly-Si gate electrode and HfO/sub 2/ gate dielectric were fabricated using a conventional self-aligned process flow. Functional transistors with final EOT/spl sim/1.8 nm were obtained down to 70 nm gate lengths using a low thermal budget process without a poly re-oxidation step. Electrical data and TEM analysis indicate that lateral oxygen diffusion was not an issue in EOT degradation. An asymmetric V/sub FB/ shift is observed for NMOS and PMOS transistors. The drive current for transistors with a high-k gate dielectric is improved by 10-15% with gate length scaling, but even for 70 nm gate length transistors it reaches only 60% of the SiON currents.

Interface passivation mechanisms in metal gated oxide capacitors

We use the conductance technique to measure the density of interface states, D/sub it/, in MOS capacitors with metal gate electrodes. D/sub it/ as a function of the band gap is extracted for a series of capacitors. ALD TiN electrodes show poor passivation while PVD TaN electrodes do not. There is no evidence that the poor passivation in the TiN electrodes is because of low hydrogen diffusion through the metal oxide stack. Possibly, the strain induced by the ALD metal layer or contamination from the metal precursors are responsible for the poor passivation.

A new method to calculate leakage current and its applications for sub-45nm MOSFETs

This paper proposes a new quantum mechanical model for the calculation of leakage currents. The model incorporates both variational calculus and the transfer matrix method to compute the subband energies and the life times of the inversion layer states. The use of variational calculus simplifies the subband energy calculation due to the analytical form of the wave functions, which offers an attractive perspective towards the calculation of the electron mobility in the channel. The model can be extended to high-k dielectrics with several layers. Good agreement between experimental data and simulation results is obtained for metal gate capacitors.