Jacob Hooker

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

We demonstrate for the first time the performance of aggressively scaled triple gate devices with a MOCVD TiN/HfO gate stack. The transistors have physical gate lengths down to 40 nm, and 60 nm tall and 10 nm wide fins. We show that MOCVD TiN can be used to successfully set the threshold voltage of both nMOS and pMOS devices in the range of |0.4-0.5| V. Devices with excellent Ion/Ioff behavior were obtained with reduced gate leakage values.

ALD of Ta(Si)N Thin Films Using TDMAS as a Reducing Agent and as a Si Precursor

Ta(Si)N thin films were deposited by atomic layer deposition (ALD) from tantalum chloride, ammonia, and tris(dimethylamino)silane (TDMAS). TDMAS was used as a reducing agent and as a silicon precursor. The pulsing order and the length of the TDMAS pulse were optimized. The deposition temperature was varied between 300 and 500°C. The film properties were analyzed by time-of-flight elastic recoil detection analysis, energy dispersive X-ray spectroscopy, X-ray diffraction, and the standard four-point probe method. Additionally work function values were measured by depositing 50 nm thick Ta(Si)N films on different thicknesses of hafnium oxide layers on silicon.

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La₂O₃, Dy₂O₃ and Al₂O₃ on both HfSiO(N) and SiO₂ to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

Te-induced modulation of the Mo/HfO2 interface effective work function

First principles calculations of the impact of Te local doping on the effective work function of a Mo∕HfO2 interface are presented. The undoped interface has a p-type effective work function. We find that interstitial Te and Te in the metal both make the effective work function more p-type. More importantly, Te substituting for O or Hf in the dielectric near the interface—energetically stable for all growth conditions—decreases the effective work function, making it more n-type.

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

Investigation on Molybdenum and Its Conductive Oxides as p-Type Metal Gate Candidates

In this work, we studied molybdenum (Mo) and its conductive oxides (MoO x ) for p-type metal gate application. Three compositions of MoO x have been investigated. The resistivity of Mo/MoO x was found to significantly increase with the oxygen incorporation. A clear phase separation of all MoO x compositions was observed after high-temperature thermal treatment. The incorporation of oxygen was found to be effective to increase the work function (WF) of Mo. However, after full device integration, a significant WF decrease of MoO x was observed, which may be induced during the high-temperature junction activation process. This high-temperature process also led to a significant interfacial silicon oxide layer growth for MoO x gated stacks. The equivalent oxide thickness dependent flatband voltage roll-off behavior and gate leakage will also be discussed.

Tuning PMOS Mo(O,N) metal gates to NMOS by addition of DyO capping layer

Abstract MoON has been reported to be a good PMOS candidate. In this paper, we report tuning of the MoON PMOS metal towards Si conduction band-edge with Vtau as low as 0.35V for SiON capped with DyO, using a standard high temperature gate first process flow. Consistent shifts of 450 mV in VFB and Vtau are observed by capping SiON with DyO for MoON gate. Gate leakage as low as 10-7 A/cm2 at 17.6A EOT is obtained, outperforming HfSiON by 3 orders of magnitude. Intermixing of SiON and DyO is shown to be the key element leading to low EOT and low gate leakage without any degradation of the gate oxide integrity.