Guillaume Pailloncy

High-Frequency Noise Performance of 60-nm Gate-Length FinFETs

In this paper, the first-ever published investigation on radio-frequency (RF) noise performance of FinFETs is reported. The impact of the geometrical dimensions of FinFETs on RF noise parameters such as the channel length, the fin width, as well as the fin number is analyzed. A minimum noise figure of 1.35 dB is obtained with an associated available gain of 13.5 dB at 10 GHz for Vdd = 0.5 V. This result is quite encouraging to bring solutions for future low-power RF systems.

Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs

Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucels noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f/sub max/) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs.

High-Frequency and Noise Performances of 65-nm MOSFET at Liquid Nitrogen Temperature

In this paper, the high-frequency properties of MOSFETs at low-temperature operation are investigated through measurements and electrical simulations. The experimental results show that the device achieves a 335-GHz fmax and a 300-GHz ft when operating at low temperature (78 K), which constitutes, respectively, a 78% and 34% improvement compared to the room temperature performances (296 K). The minimum noise figure NFmin decreases from 1.4 dB (296 K) to 0.5 dB at 30 GHz (78 K), while the associated gain increases from 8 to 12 dB

Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk

Frequency variation of the output conductance in advanced fully depleted SOI and multiple-gate MOSFETs related to the electrical coupling between drain and Si substrate underneath the buried oxide (BOX) is analyzed through measurements and 2-D simulations. A low-frequency (LF) conductance variation in these devices, which could be erroneously attributed to the self-heating effect, is proved to be related to the presence of the Si substrate underneath the BOX. Suppression of this substrate-related LF transition in narrow-fin FinFETs output conductance is experimentally demonstrated. Furthermore, the substrate-related transitions are shown to be increasing with device downscaling, as well as BOX thinning, suggesting that this effect becomes more important for the future device generations

Static and High-Frequency Behavior and Performance of Schottky-Barrier p-MOSFET Devices

The dc and radio-frequency performance of 85-nm gate-length p-channel PtSi source/drain Schottky-barrier MOSFETs on two wafers with differing source/drain silicide anneal temperatures has been investigated. ON currents of 545 mA/ mm and transconductances of 640 mS/mm are presented for bias conditions based on recommendations by the International Technology Roadmap for Semiconductors. Devices receiving silicide anneals at lower temperatures exhibit higher drive currents and transconductances, which is attributed to a lower Schottky barrier between source and channel. Unity-gain cutoff frequencies of up to 71 GHz are measured, which is considerably higher than comparable doped source/drain pMOS devices reported in literature. Improved high-frequency performance is attributed to high transconductance and low capacitance.

Substrate Effect on the output conductance frequency response of SOI MOSFETs

The paper analyzes the influence of the Si substrate on the AC characteristics of silicon-on-insulator (SOI) MOSFETs through 2D Atlas simulations and measurements. It is shown that the presence of the Si substrate underneath the buried oxide (BOX) results in two transitions in the frequency response of the output conductance, caused by the variation of the potential at substrate-BOX interface. A first-order small-signal model is proposed to support the obtained results. It is demonstrated that the appearance of “substrate-related” transitions, their position and amplitude depend strongly on the substrate doping, space-charge conditions at substrate-BOX interface, temperature and moreover become more pronounced with device downscaling.

New de-embedding technique based on Cold-FET measurement

In this paper, we present a new de-embedding technique which does not require any dedicated RF test structure. This leads to great reduction of surface area on the wafer. Furthermore, this technique allows us to break through the re-contacting and dispersion problems that might affect the RF performance accuracy of future devices

Noise modeling and performance in 0.15-μm fully depleted SOI MOSFET

This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.

Impact of down scaling on high frequency noise performance of bulk and SOI MOSFETs

Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucels noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f/sub max/) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs.

Linear, Noise and Nonlinear HF Models for Advanced CMOS Technology

Deep CMOS technology requires more and more accurate and robust RF CMOS models (PSP, BSIM, EKV...) for circuit design, predictable down to millimetrique wave range. Because of their scalability, these models are the more convenient ones, their major drawback being the huge number of parameters to experimentally extract, which is costly and time consuming. Hence, whenever CMOS technology is under development, it looks interesting to investigate another approach. For this purpose, we propose in this work to show the usefulness of several in-house RF oriented models, fast to extract, to investigate the AC and noise properties of a 65 nm bulk CMOS technology. An extension is also proposed through the presentation of a large signal model, for which an application was carried out considering a 130 nm CMOS SOI technology