Dimitri Lederer

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.

RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

In this paper, we investigate the impact of a passivation layer on the performance of a commercial high-resistivity (HR) SOI CMOS technology. The passivation layer consists of a 300-nm-thick polysilicon cover located directly below the buried oxide (BOX). Both passive and active devices are studied. It is demonstrated that substrate passivation completely suppresses substrate losses that are usually induced by parasitic surface conduction at the substrate/BOX interface in oxidized HR Si substrates. We also report no effect of the underlying polysilicon on the dc and RF behavior of MOSFETs devices. The results shown here strongly suggest that substrate passivation using polysilicon is a promising tool to eradicate substrate losses in HR SOI wafers, thereby increasing the performance of functional SOI logic and high-speed circuits.

Dependence of finFET RF performance on fin width

This work analyzes the radio frequency (RF) performance of 60-nm gate length finFETs, for which the DC behavior exhibits reduced SCE. The RF analysis is carried out as a function of the gate length as well as the fin width (Wfin). Cut off frequencies (ft, f max) on the order of 100 GHz are reported for the first time. It is shown that Wfin has a large impact on those frequencies, due mainly to its effect on the access resistances. Nevertheless, it is also demonstrated that using optimized layout geometry, fmax values close to 170 GHz are to be expected

High-Frequency Noise Performance of 60-nm Gate-Length FinFETs

In this paper, the first-ever published investigation on radio-frequency (RF) noise performance of FinFETs is reported. The impact of the geometrical dimensions of FinFETs on RF noise parameters such as the channel length, the fin width, as well as the fin number is analyzed. A minimum noise figure of 1.35 dB is obtained with an associated available gain of 13.5 dB at 10 GHz for Vdd = 0.5 V. This result is quite encouraging to bring solutions for future low-power RF systems.

Perspective of FinFETs for analog applications

FinFETs are known to be one of the most promising technological solutions to create high-performance ultra-scaled Si MOSFETs. In this paper, we present the first detailed experimental investigation of the analog performance of FinFETs with channel lengths down to 50 nm. We demonstrate that such devices have very strong potential for analog applications, mainly thanks to a super-high value of the Early voltage and hence intrinsic gain, which they can provide. The impact of fin width on device characteristics is also analysed. We show that the narrowest devices appear as the most promising, since they operate in the fully-depleted regime, even possibly in volume inversion.

Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs

This paper investigates the influence of the silicon substrate on the ac characteristics of silicon-on-insulator (SOI) MOSFETs. It is shown for the first time that the presence of the substrate underneath the buried oxide results in two transitions (i.e., zero-pole doublets) in the frequency response of the output conductance. It is demonstrated that the appearance of these transitions, the position and amplitude of which strongly depend on the substrate doping, is caused by the variation of the potential at substrate-buried oxide interface, which we call the Floating Effective Back-Gate (FEBG) effect. A first-order small-signal equivalent circuit is proposed to support our observations.

Enhanced high resistivity SOI wafers for RF applications

In this work, we investigate the impact of distinctly processed trap-rich layers of polysilicon inserted between BOX and HR Si substrate on the effective resistivity, substrate losses and crosstalk level in HR SOI wafers. The wafers were fabricated starting from p-type high resistivity bulk wafers with resistivity higher than 3 k/spl Omega/.cm. The wafers were first covered with a LPCVD layer of undoped polysilicon at 2 distinct temperatures (T/sub poly/=585 /spl deg/C, 625 /spl deg/C) and with varying thickness. This layer was afterwards passivated with a charge rich 3 /spl mu/m thick PECVD oxide of the reference wafer. The oxide layer was densified by RTA at 800 /spl deg/C during 20 s.

Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk

Frequency variation of the output conductance in advanced fully depleted SOI and multiple-gate MOSFETs related to the electrical coupling between drain and Si substrate underneath the buried oxide (BOX) is analyzed through measurements and 2-D simulations. A low-frequency (LF) conductance variation in these devices, which could be erroneously attributed to the self-heating effect, is proved to be related to the presence of the Si substrate underneath the BOX. Suppression of this substrate-related LF transition in narrow-fin FinFETs output conductance is experimentally demonstrated. Furthermore, the substrate-related transitions are shown to be increasing with device downscaling, as well as BOX thinning, suggesting that this effect becomes more important for the future device generations

Properties of Accumulation-Mode Multi-Gate Field-Effect Transistors

In this work, we analyze the conduction mechanisms and the electrical performance of intrinsic and doped accumulation-mode (AM) p-type, triple-gate silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFETs). Both long- and short-channel devices with different fin widths are investigated on the basis of experimental and simulation data. The analysis shows that for a small fin width, the threshold voltages associated with both body current and side channels in heavily doped devices coincide, thereby preventing the increase in leakage current caused by body conduction that is conventionally observed in planar AM fully-depleted (FD) SOI MOSFETs. Shortchannel effects (SCEs) are minimized in these devices owing to the good electrostatic control by the surrounding gate. The experimental data indicate that SCEs are comparable to those observed in inversion-mode (IM) devices with a gate length of 50 nm. This makes AM triple-gate (or more generally, multigate) MOSFETs interesting devices for digital applications.