N. Paulino

Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme

Since the 1970s, the analog switches in switched-capacitor (SC) circuits are operated by nonoverlapping bi-phase control signals (/spl phi//sub 1/, /spl phi//sub 2/). The nonoverlapping of these two phases is essential for successful SC operation since, a capacitor inside an SC circuit can discharge if two switches, driven by /spl phi//sub 1/ and /spl phi//sub 2/, are turned on simultaneously. Moreover, since 1983, two additional phases are generally used in many SC circuits, which consist of advanced versions of /spl phi//sub 1/ and /spl phi//sub 2/. These two additional phases overcome the problem of signal-dependent charge injection. This paper presents a low-power and low-voltage analog-to-digital (A/D) interface module for biomedical applications. This module provides an A/D conversion based on a mixed clock-boosting/switched-opamp (CB/SO) second-order sigma-delta (/spl Sigma//spl Delta/) modulator, capable of interfacing with several different types electrical signals existing in the human body, only by re-programming the output digital filter. The proposed /spl Sigma//spl Delta/ architecture employs a novel single-phase scheme technique, which improves the dynamic performance and highly reduces the clocking circuitry complexity, substrate noise and area. Simulated results demonstrate that the signal integrity can be preserved by exploring the gap between the high conductance region of pMOS and nMOS switches at low power-supply voltages and the fast clock transitions that exist in advanced CMOS technologies. The mixed CB/SO architecture together with the overall distortion reduction resulting from using the proposed single-phase scheme, result that the dynamic range of the modulator is pushed closer to the theoretical limit of an ideal second-order /spl Sigma//spl Delta/ modulator.

A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency

A 1.5V 10-b 50MS/s 2-channel pipeline ADC is described. Amplifiers arc efficiently shared between channels using low-voltage techniques to reduce the power supply. The selected resolution per stage avoids the need of scaling the stages, simplifying the implementation of a low-power design. Measurements from the prototypes fabricated in a 0.18 /spl mu/m CMOS technology exhibit 10b DNL, 9.5b INL and 9.2 effective bits at Nyquist-rate. The chip occupies 1.3 mm/sup 2/ and dissipates only 29 mW at 1.5V.

Design of a spiral-mode microstrip antenna and matching circuitry for ultra-wide-band receivers

The expanding use of wireless devices has prompted the need of larger bandwidths by these devices. This need is a result of larger bit-rates or the use of different standards using different frequency bands. In this work, the design and test of a wide band antenna and its matching circuit is presented The wide band antenna is of the Archimedes type because it has a compact size and can be easily manufactured using inexpensive PCB technology. The possibility of including the matching circuitry in the same PCB is also studied.

A general-purpose kernel based on genetic algorithms for optimization of complex analog circuits

This paper presents general-purpose kernel based genetic algorithms for optimizing complex analog circuits and systems. The developed tool is very flexible allowing optimizations at different levels of abstraction. The optimization of any new block is basically carried-out by simply providing two additional files to the kernel. A text file containing the information of the genes (variables) of the chromosome and, on the other hand, a dynamic link library (DLL) type file, which is obtained by compiling a C++ code-source file comprising the overall fitness function. Optimization examples of two low-voltage circuits clearly assess the attractiveness of this tool.

On-chip built-in self-test of video-rate ADCs using Gaussian noise

This paper presents a new method to perform built-in-self-test (BIST) to measure the DNL, INL and the output noise of an ADC. The technique uses a Gaussian noise source as input stimulus and a simple algorithm based in precalculated tables (on-chip ROMs) for the DNL and INL tests. The results of the proposed BIST algorithm are compared with other standard tests. The simplicity of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.

Switched-capacitor circuits using a single-phase scheme

A novel single phase scheme for use in switched-capacitor (SC) circuits is described. Signal integrity is preserved by exploring the gap between the high conductance region of PMOS and NMOS switches at low power-supply voltages and the fast clock transitions that exist in advanced CMOS technologies. In order to illustrate the attractiveness of the proposed scheme, two practical circuit examples are presented. Electrical simulated results of a low-voltage 2/sup nd/-order /spl Sigma//spl Delta/ modulator clearly demonstrate the improvements in terms of harmonic distortion that can be achieved using this technique.

On-Chip Built-In Self-Test of Video-Rate ADCs Using a 1.5 V CMOS Gaussian Noise Generator

A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.