Gunter Schoof

Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays

The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor - 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage VWL = 1.4 V and a bitline (BL) voltage VBL = 2.3 V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of 10 μs (VWL = 1.4 V and VBL = 3.5 V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition during array processing, are those subject to poor switching performance, larger variability, and faster wear out. Devices formed by a pulse-retry algorithm show: 1) shorter endurance and 2) higher variability during cycling.

Design methodology for fault tolerant ASICs

The sensitivity of application specific integrated circuits (ASICs) to the single event effects (SEE) can induce failures of the systems which are exposed to increased radiation levels in the space and on the ground. This paper presents a design methodology for a full fault tolerant ASIC that is immune to the single event upsets (SEU) in sequential logic, the single event transients (SET) in combinational logic and the single event latchup (SEL). The dual modular redundancy (DMR) and a SEL power-switch (SPS) are the basis for a modified ASIC design flow. Measurement results have proven the correct functionality of DMR and SPS circuits, as well as a high fault tolerance of implemented ASICs along with moderate overhead in respect of power consumption and occupied silicon area.

SEU and SET fault injection models for fault tolerant circuits

In this paper we describe the fault injection models for the systems tolerant to the single event upsets (SEU) and single event transients (SET). The presented fault modelling approach is based on the random generated SEU faults in sequential logic and SET faults in combinational logic. The fault injection models for triple modular redundant (TMR) and dual modular redundant (DMR) circuits are developed in order to simulate the fault-tolerant systems. The analytical models for calculation of the probability of failure-free TMR and DMR circuits are defined too. To justify the reduced redundancy concept, the simulated and calculated probabilities of failure-free TMR and DMR circuits are presented and discussed. The obtained results show a better trade-off between hardware overhead and circuit failure-free probability of the DMR concept.

Fault-tolerant ASIC Design for High System Dependability

Fault-tolerant devices are becoming more and more important in safety-critical applications. In addition, because of further decreased geometries, integrated circuits are becoming more susceptible to induced interference. This paper presents new methods and design concepts to make application specific integrated circuit (ASIC) devices fault-tolerant to effects generated in the harsh automotive environment, especially to single event effects (SEEs). We describe how to mitigate single event effects which can immediately affect the function of electronic components. ASICs provided with this technique will increase the reliability and dependability while simultaneously maintaining the full real-time behaviour of the system.

LEON-2: General Purpose Processor for a Wireless Engine

The paper presents a case study on the implementation of LEON-2 processor system on a chip. LEON-2 core is used as a general purpose processor for the concept of high-performance low-power wireless engine. The implemented processor system has been verified and become a reusable module of our modular library. The measured speed and power consumption of implemented system on a chip prove LEON-2 processor is a good processor candidate for the target application

Fault-tolerant TMR and DMR circuits with latchup protection switches

Abstract The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor.

Network Centric Systems for Space Applications

Serious problems we face within avionics development of every new spacecraft are: the huge cost and long development time due to the interfaces specification, which has to be written and specified for every satellite from scratch. Furthermore we must consider the extremely high costs and almost no post-development reuse of the board computer. Our strategy is what we call network centric computing. We aim to create a spacecraft area network (SCAN) to which all devices and computers are attached. We aim to create a high speed interconnection link definition, which is so simple that it can be implemented and used by each and every one. We have already developed reference implementations, which will be distributed as open source for both field programmable gate array (FPGA) intellectual property (IP) cores and software middleware. The presented SCAN middleware switch is currently in development in Europe as an application specific integrated circuit (ASIC).

Integrated Single Event Latchup protection for ASICs used in space applications

The paper presents a protection technique for CMOS ASIC designs, based on the integrated Single Event Latchup (SEL) protection. Triple or double modular redundancy, together with integrated SEL protection switches (SPS) make the base for the fault-tolerant ASICs, able to operate in space environment. The presented approach represents a cheap solution, based on standard non-radiation hardened process. The SPS has been designed, characterized and verified in both standard and radiation environment. The proposed protection technique requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. The concept has been verified on silicon.

A System-On-Chip for Wireless Body Area Sensor Network Node

The paper describes the design, implementation, and verification of a system-on-chip aimed to play the role of a general purpose processor for a wireless body area sensor network node. The heart of the sensor node is the IPMS430 processor core. This processor core is a clone of the Texas Instruments MSP430 microcontrollers central processing unit. The implemented and verified system includes the processor core, program and data memories, timer, input/output port, and interrupt chain. The paper ends presenting electrical and physical features of the implemented system-on-chip.

Redundant circuits with latchup protection

The paper presents triple and double modular redundant (TMR and DMR) circuits with the latchup protection. Additional logic has been designed to control the latchup protection phase and different power domains. An analytical model for the failure-free probability estimation has been developed too. Test circuits have been implemented and simulated.