Guoyun Tian

Corner bonding of CSPs: processing and reliability

The use of chip-scale packages (CSPs) has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow provide the most common solution to improving mechanical reliability. However, capillary underfill dispense, flow, and cure steps and the associated equipment add cost and complexity to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print but before CSP placement. During reflow, the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement, and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and nonunderfilled CSPs. Finite-element modeling results for the drop test are also included.

Lead-free chip scale packages: assembly and drop test reliability

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.

Ultra-High Reliability Flip Chip on Laminate For Harsh Environments

In this work, we report on our efforts to develop ultra-high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. -55 to 150 degC). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and unpressurized space applications

Risk Management Models for Flip-Chip Electronics in Extreme Environments

In this work, risk-management and decision-support models for reliability prediction of flip chip packages in harsh environments have been presented. The models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing product designs for minimal risk insertion of new packaging technologies. In addition, qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. Previous studies have focused on development of modeling tools at sub-scale or component level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Multivariate linear regression and robust principal components regression methods were used for developing these models. The first approach uses the potentially important variables from stepwise regression, and the second approach uses the principal components obtained from the eigen-values and eigen-vectors, for model building. Principal-component models have been included because if their added ability in addressing multi-collinearity. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Statistical models developed in the present work are based on failure data collected from the published literature and extensive accelerated test reliability database in harsh environments, collected by center of advanced vehicle electronics. Sensitivity relations for geometry, materials, and architectures based on statistical models, failure mechanics based closed form models and FEA models have been developed. Convergence of statistical, failure mechanics, and FEA based model sensitivities with experimental data has been demonstrated.© 2006 ASME

Drop Reliability of Corner Bonded CSP in Portable Products

The use of CSPs has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow, provide the most common solution to improving mechanical reliability. However, capillary underfill adds board dehydration, underfill dispense, flow and cure steps and the associated equipment to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print, but before CSP placement. During reflow the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and non-underfilled CSPs. Finite element modeling results for the drop test are also included.Copyright

Drop-Impact Reliability of Chip-Scale Packages in Handheld Products

The use of CSPs has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow, provide the most common solution to improving mechanical reliability. However, capillary underfill adds board dehydration, underfill dispense, flow and cure steps and the associated equipment to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print, but before CSP placement. During reflow the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and non-underfilled CSPs. Finite element modeling results for the drop test are also included.© 2003 ASME

Nano-Underfills for High-Reliability Applications in Extreme Environments

Silica particles are used as a filler material in electronic underfills to reduce coefficient of thermal expansion of the underfill-epoxy matrix. In traditional underfills, the size of silica particles is in the micrometer range. Reduction in particle sizes into the nanometer range has the potential of attaining higher volume fraction particle loading in the underfills and greater control over underfill properties for higher reliability applications. Presently, no-flow underfills have very low or no filler content because micron-size filler particles hinder solder joint formation. Nano-silica underfills have the potential of attaining higher filler loading in no-flow underfills without hindering solder interconnect formation. In this paper, property prediction models based on representative volume element (RVE) and modified random spatial adsortion have been developed. The models can be used for development of nano-silica underfills with desirable thermo-mechanical properties. Temperature dependent thermo-mechanical properties of nano-underfills have been evaluated and correlated with models in a temperature range of -175degC to 150degC. Properties investigated include, temperature dependent stress-strain, creep and stress relaxation behavior. Nano-underfills on 63Sn37Pb eutectic and 95.5Sn3.5Ag1.0Cu leadfree flip-chip devices have been subjected to thermal shock tests in the range of -55degC to 125degC and -55degC to 150degC, respectively. The trade-offs between using nano-fillers instead of micron-fillers on thermo-mechanical properties and reliability has been benchmarked.

Temperature and Time-dependent Property Prediction and Validation for Nano-Underfills using RSA based RVE Algorithms

Presently, no-flow underfills have very low or no filler content because micron-size filler particles hinder solder joint formation. Nano-silica underfills have the potential of attaining higher filler loading in no-flow underfills without hindering solder interconnect formation (Kraszewshi et al., 2001 and Shi and Wong, 1999). The silica particles reduce coefficient of thermal expansion of the underfill-epoxy matrix. In traditional underfills, the size of silica particles is in the micrometer range. In this paper, property prediction models based on representative volume element (RVE) and modified random spatial adsorption (RSA) have been developed. The models utilize statistically isotropic random-placement of nano-particles, in addition to random size-distribution of particles for analysis of material. Volume fractions up to 40 percent of nano-silica filler have been studied. Properties predicted and correlated with experimental data include, coefficient of thermal expansion, elastic modulus, poissons ratio, and viscoelastic properties including stress relaxation under applied strain. All properties have been measured in the temperature range of -175 degC to +150degC. Nano-underfills with 10 percent and 22 percent volume fraction of filler assembled with 63Sn37Pb eutectic and 95.5Sn3.5Ag1.0Cu leadfree flip-chip devices have been subjected to thermal shock tests in the range of -55 to 125degC and -55 to 150degC respectively. The trade-offs between using nano-fillers instead of micron-fillers on thermo-mechanical properties and reliability has been benchmarked

Nano-Underfills for Fine-Pitch Electronics

Packaging materials undergo dimensional changes under environmental exposure to temperature change. Thermomechanical cyclic loads induce stresses and damage interconnects. Underfills compensate for the mismatch in coefficient of thermal expansion (CTE) between silicon and the printed circuit board (PCB), and have been used as a supplemental restraint mechanism to enhance the reliability for flip-chip devices and chip-scale packages in a wide variety of applications including portable consumer electronics such as cellular phones, laptops, under-the-hood electronics, microwave applications, system in package (SIP), high-end workstations, and several other high-performance applications. Figure 14.1 shows an underfilled flip-chip assembly, with solder interconnects between the silicon chip and the PCB. It surrounds the solder balls. Underfill technology has evolved to meet the demand of decreasing feature size and increasing input/output (I/O) number in the integrated circuit (IC) chip.

High Reliability Flip Chip Using Low CTE Laminate Substrates

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. −55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR® ). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.Copyright