Gustavo Liñán-Cembrano

ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs

Today, with 0.18-/spl mu/m technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-/spl mu/m technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-/spl mu/m standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3/spl times/3 neighborhoods in less than 1.5 /spl mu/s, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 /spl mu/s, and CNN-like temporal evolutions with a time constant of about 0.5 /spl mu/s. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

Effects of network modularity on the spread of perturbation impact in experimental metapopulations

Modularity limits disturbance effects The networks that form natural, social, and technological systems are vulnerable to the spreading impacts of perturbations. Theory predicts that networks with a clustered or modular structure—where nodes within a module interact more frequently than they do with nodes in other modules—might contain a perturbation, preventing it from spreading to the entire network. Gilarranz et al. conducted experiments with networked populations of springtail (Folsomia candida) microarthropods to show that modularity limits the impact of a local extinction on neighboring nodes (see the Perspective by Sales-Pardo). In networks with high modularity, the perturbation was contained within the targeted module, and its impact did not spread to nodes beyond it. However, simulations revealed that modularity is beneficial to the network only when perturbations are present; otherwise, it hinders population growth. Science, this issue p. 199; see also p. 128 Networks of springtail (Folsomia candida) microarthropods are more robust to perturbation when organized in modules. Networks with a modular structure are expected to have a lower risk of global failure. However, this theoretical result has remained untested until now. We used an experimental microarthropod metapopulation to test the effect of modularity on the response to perturbation. We perturbed one local population and measured the spread of the impact of this perturbation, both within and between modules. Our results show the buffering capacity of modular networks. To assess the generality of our findings, we then analyzed a dynamical model of our system. We show that in the absence of perturbations, modularity is negatively correlated with metapopulation size. However, even when a small local perturbation occurs, this negative effect is offset by a buffering effect that protects the majority of the nodes from the perturbation.

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone mapping algorithm during image capture operation. The histogram of the previous frame of an auxiliary image, which contains time stamp information, is employed as an estimation of the probability of illuminations impinging pixels at the present frame. The compression function of illuminations, namely tone mapping curve, is calculated using this histogram. A QCIF resolution proof-of-concept prototype has been fabricated using a 0.35 μm opto-flavored standard technology. The sensor is capable of mapping scenes with a maximum intra-frame dynamic range of 151 dB (25 bits/pixel in linear representation) by compressing them to only 7 bits/pixel, while keeping visual quality in details and contrast. The in-pixel on-the-fly fully parallel tone mapping achieves high-frame rate allowing real-time high dynamic range video (120 dB at 30 frames/s).

Hairiness: the missing link between pollinators and pollination

Background Functional traits are the primary biotic component driving organism influence on ecosystem functions; in consequence, traits are widely used in ecological research. However, most animal trait-based studies use easy-to-measure characteristics of species that are at best only weakly associated with functions. Animal-mediated pollination is a key ecosystem function and is likely to be influenced by pollinator traits, but to date no one has identified functional traits that are simple to measure and have good predictive power. Methods Here, we show that a simple, easy to measure trait (hairiness) can predict pollinator effectiveness with high accuracy. We used a novel image analysis method to calculate entropy values for insect body surfaces as a measure of hairiness. We evaluated the power of our method for predicting pollinator effectiveness by regressing pollinator hairiness (entropy) against single visit pollen deposition (SVD) and pollen loads on insects. We used linear models and AICC model selection to determine which body regions were the best predictors of SVD and pollen load. Results We found that hairiness can be used as a robust proxy of SVD. The best models for predicting SVD for the flower species Brassica rapa and Actinidia deliciosa were hairiness on the face and thorax as predictors (R2 = 0.98 and 0.91 respectively). The best model for predicting pollen load for B. rapa was hairiness on the face (R2 = 0.81). Discussion We suggest that the match between pollinator body region hairiness and plant reproductive structure morphology is a powerful predictor of pollinator effectiveness. We show that pollinator hairiness is strongly linked to pollination—an important ecosystem function, and provide a rigorous and time-efficient method for measuring hairiness. Identifying and accurately measuring key traits that drive ecosystem processes is critical as global change increasingly alters ecological communities, and subsequently, ecosystem functions worldwide.

Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor

This paper presents Wi-FLIP, a vision-enabled WSN node resulting from the integration of FLIP-Q, a prototype vision chip, and Imotel, a commercial WSN platform. In Wi-FLIP, image processing is not only constrained to the digital domain like in conventional architectures. Instead, its image sensor — the FLIP-Q prototype — incorporates pixel-level processing elements (PEs) implemented by analog circuitry. These PEs are interconnected, rendering a massively parallel SIMD-based focal-plane array. Low-level image processing tasks fit very well into this processing scheme. They feature a heavy computational load composed of pixel-wise repetitive operations which can be realized in parallel with moderate accuracy. In such circumstances, analog circuitry, not very precise but faster and more area- and power-efficient than its digital counterpart, has been extensively reported to achieve better performance. The Wi-FLIPs image sensor does not therefore output raw but pre-processed images that make the subsequent digital processing much lighter. The energy cost of such pre-processing is really low — 5.6mW for the worst-case scenario. As a result, for the configuration where the Imote2s processor works at minimum clock frequency, the maximum power consumed by our prototype represents only the 5.2% of the whole system power consumption. This percentage gets even lower as the clock frequency increases. We report experimental results for different algorithms, image resolutions and clock frequencies. The main drawback of this first version of Wi-FLIP is the low frame rate reachable due to the non-standard GPIO-based FLIPQ-to-Imote2 interface.

ACE16k based stand-alone system for real-time pre-processing tasks

This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The systems architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.

A processing element architecture for high-density focal plane analog programmable array processors

The architecture of the elementary Processing Element - PE - used in a recently designed 128/spl times/128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3/spl times/3 convolution masks. The vision chip has been implemented in a standard 0.35 /spl mu/m CMOS technology. The main PE related figures are: 180 cells/mm/sup 2/, 18 MOPS/cell, and 180 /spl mu/W/cell.

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips

This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15@mm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.

A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V.

Incubating terns modify risk-taking according to diurnal variations in egg camouflage and ambient temperature

Studies of risk-taking by breeding birds have frequently addressed the effect of brood value on the decisions taken by incubating birds when predators approach their nests. However, leaving eggs unattended during predator disturbance may expose embryos to other potentially harmful factors, to which parent birds should respond when making decisions about when to leave or return to their nest. In this study, we show that diurnal changes in flushing behaviour of incubating terns from nests during predator approach were affected by egg camouflage, the terns allowing a closer approach to individual nests when the eggs appeared better camouflaged. Return times to the nests were affected by ambient temperature, with the terns shortening such times at high ambient temperatures, thus diminishing the risk of egg overheating. As a whole, our results show that the decisions of the birds on when to leave or return to their nests depended on shifting payoffs, as a consequence of diurnal variations in both the thermal risks incurred by embryos and egg crypsis. Environmental costs of risk-taking, such as those considered here, should be addressed in studies of risk-taking by breeding birds. This type of study may have implications for our knowledge of cognitive processes that affect risk-taking.Significance statementWhen a predator approaches a nest, the incubating bird has to decide at which moment to leave the nest, which may be affected by environmental factors that may hamper embryo viability. We studied flushing/returning behaviour of incubating little terns Sternula albifrons in response to disturbance and show that risk-taking was affected by the occurrence of simultaneous environmental threats according to shifting fitness payoffs. When the eggs appeared better camouflaged, which usually occurred around midday, the terns allowed closer approach to individual nests. The terns shortened the return to their nests with increasing ambient temperature, which took place at midday. Thus, our results show that, by adjusting their responses to shifting payoffs, the terns modulated the risks incurred by their offspring, as eggs were less time exposed to direct solar radiation in midday, when the risk of overheating was higher.