Elisenda Roca

An Integrated Layout-Synthesis Approach for Analog ICs

In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.

A memetic approach to the automatic design of high-performance analog integrated circuits

This article introduces an evolution-based methodology, named memetic single-objective evolutionary algorithm (MSOEA), for automated sizing of high-performance analog integrated circuits. Memetic algorithms may achieve higher global and local search ability by properly combining operators from different standard evolutionary algorithms. By integrating operators from the differential evolution algorithm, from the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes in handling analog circuit design problems with numerous and tight design constraints. The method has been tested through the sizing of several analog circuits. The results show that design specifications are met and objective functions are highly optimized. Comparisons with available methods like genetic algorithm and differential evolution in conjunction with static penalty functions, as well as with intelligent selection-based differential evolution, are also carried out, showing that the proposed algorithm has important advantages in terms of constraint handling ability and optimization quality.

Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits

This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.

Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors

In this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable.

MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips

This work has been founded by NICOP Grant N68171-98-C-9004 and CICYT Grant No. TIC96-1392-C02-02.

Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview

This paper reviews the application of evolutionary computation techniques to analog, mixed-signal and radio-frequency design problems. Design needs, limitations of existing approaches and open challenges are pointed out.

CNNUC3: a mixed-signal 64/spl times/64 CNN universal chip

This paper describes the general characteristics of a prototype implementation of a 64/spl times/64 cells Cellular Neural Network (CNN) with enhanced functionalities in the direction of the CNN Universal Chip concept. The mixed-signal prototype has been designed and manufactured in a CMOS 0.5 /spl mu/m technology. It is conceived to be the core component of a new class of video-processing systems for advanced multimedia applications.

Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors

In this paper, the application of multi-objective evolutionary algorithms to the evaluation of performance trade-offs of planar inductors, an almost ubiquitous device in radio-frequency microelectronics, is studied. The absence of appropriate stopping criteria in most evolutionary algorithms reveals to be critical in this application. A new stopping criterion based on monitoring a set of performance metrics that account for convergence and diversity is proposed and demonstrated with practical radio-frequency circuit design problems.

ACE16k based stand-alone system for real-time pre-processing tasks

This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The systems architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.

A simplification before and during generation methodology for symbolic large-circuit analysis

This paper introduces our original implementation of the combination of simplification before and during generation techniques to enable the approximated symbolic analysis of large analog circuits. Special emphasis is paid to the circuit reduction techniques embedded in the simplification before generation module. Experimental results of the application of the symbolic analysis methodology are shown which demonstrate its capability to provide interpretable symbolic expressions.