Gyorgy Vizkelethy

Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs

The statistical transient response of floating body SOI and bulk devices is measured under proton and heavy ion irradiation. The influence of the device architecture is analyzed in detail for several generations of technologies, from 0.25 mum to 70nm. The effects of the measured transients on SET sensitivity are investigated. The amount of collected charge and the shape of the transient currents are shown to have a significant impact on the temporal width of propagating transients. Finally, based on our measured data, the threshold LET and the critical transient width for unattenuated propagation are calculated for both bulk and floating body SOI as a function of technology scaling. We show that the threshold LETs and the critical transient widths for bulk and floating body SOI devices are similar. Body ties can be used to harden SOI ICs to digital SET. However, the primary advantage of SOI technologies, even with a floating body design, mostly lies in shorter transients, at a given ion LET, for SOI technologies than for bulk technologies

Multiple-Bit Upset in 130 nm CMOS Technology

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates

The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design.

Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes

Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-/spl mu/m SiGe heterojunction bipolar transistors and circuits

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

Charge collection in SOI capacitors and circuits and its effect on SEU hardness

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.

Initial Assessment of the Effects of Radiation on the Electrical Characteristics of

Radiation-induced effects on the electrical characteristics of TaOx memristive (or redox) memory are experimentally assessed. 10 keV x-ray irradiation is observed to cause switching of the memristors from high to low resistance states, as well as functional failure due to cumulative dose. Gamma rays and 4.5 MeV energy protons are not observed to cause significant change in resistance state or device function at levels up to 2.5 Mrad(Si) and 5 Mrad(Si) protons, respectively. 105 MeV and 480 MeV protons cause switching of the memristors from high to low resistance states in some cases, but do not exhibit a consistent degradation. 800 keV silicon ions are observed to cause resistance degradation, with an inverse dependence of resistance on oxygen vacancy density. Variation between different devices appears to be a key factor in determining the electrical response resulting from irradiation. The proposed degradation mechanism likely involves the creation of oxygen vacancies, but a better fundamental understanding of switching is needed before a definitive understanding of radiation degradation can be achieved.

{\rm TaO}_{\rm x}

Abstract A new multidimensional high lateral resolution ion beam analysis technique, ion–electron emission microscopy (IEEM) is described. Using MeV energy ions, IEEM is shown to be capable of ion beam induced charge collection (IBICC) measurements in semiconductors. IEEM should also be capable of microscopically and multidimensionally mapping the surface and bulk composition of solids. As such, IEEM has nearly identical capabilities as traditional nuclear microprobe analysis, with the advantage that the ion beam does not have to be focused. The technique is based on determining the position where an individual ion enters the surface of the sample by projection secondary electron emission microscopy. The x – y origination point of a secondary electron, and hence the impact coordinates of the corresponding incident ion, is recorded with a position sensitive detector connected to a standard photoemission electron microscope (PEEM). These signals are then used to establish coincidence with IBICC, atomic, or nuclear reaction induced ion beam analysis signals simultaneously caused by the incident ion.

Memristive Memories

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

A new approach to nuclear microscopy: the ion–electron emission microscope

Through-wafer two-photon absorption laser experiments were performed on bulk FinFETs. Transients show distinct signatures for charge collection from drift and diffusion, demonstrating the contribution of charge generated in the substrate to the charge collection process. This result was validated through heavy ion testing on more advanced bulk FinFETs with fin widths as narrow as 5 nm. The drain region dominates the charge collection, with as much as 45 fC of charge collected in the drain region.