Gyun Yoo

Application of DBM system to overlay verification and wiggling quantification for advanced process

With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges in process control. As lithography and etch processes are pushed to get smaller dimensions, the overlay and wiggling control are hot issues due to the limiting of pattern performance. Many chip makers are using Double Patterning Technology (DPT) process to overcome design rule limitations but they are also concerned about overlay control. In DPT process, obtaining accurate overlay data by measuring overlay marks with traditional metrology is difficult because of the difference of shape and position between cell pattern and overlay marks. Cell to overlay mark miss-match will occur when there is lens aberration or mask registration error. Therefore, the best way to obtain accurate overlay data without error is to measure the real cell itself. The overlay of the cell array using DPT process can be measured by analyzing the relative position of the 2nd exposed pattern to the 1st exposed pattern. But it is not easy to clearly distinguish a 1st layer and 2nd layer in a patterned cell array image using CD SEM. The Design Based Metrology (DBM)-system can help identify which cell pattern is a 1st or 2nd layer, so overlay error between the 1st and 2nd layers at DPT process can be checked clearly. Another noticeable problem in advanced processing is wiggling. The wiggling of a pattern become severe by the etch process and must be controlled to meet electrical characteristics of what the semiconductor device requires. The 1st stage of wiggling control is to understand the level of wiggling which is crucial to device performance. The DBM-system also can be used for quantification of wiggling by determining specially designed parameters. In this paper we introduce overlay verification and wiggling quantification through new methodology for advanced memory devices.

OPC verification and hotspot management for yield enhancement through layout analysis

As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and applied to lithography field. And we have struggled not only to obtain sufficient process window with those techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot management. Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip. Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this paper, new verification methodology based on design based analysis will be introduced as an alternative method for effective control of OPC accuracy and hot spot management.

Systematic defect filtering and data analysis methodology for design based metrology

Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The major applications of DBM are OPC accuracy improvement, DFM feed-back through Process Window Qualification (PWQ) and advanced process control. In general, however, the amount of output data from DBM is normally so large that it is very hard to handle the data for valuable feed-back. In case of PWQ, more than thousands of hot spots are detected on a single chip at the edge of process window. So, it takes much time and labor to review and analyze all the hot spots detected at PWQ. Design-related systematic defects, however, will be found repeatedly and if they can be classified into groups, it would be possible to save a lot of time for the analysis. We have demonstrated an EDA tool which can handle the large amount of output data from DBM by reducing pattern defects to groups. It can classify millions of patterns into less than thousands of pattern groups. It has been evaluated on the analysis of PWQ of metal layer in NAND Flash memory device and random contact hole patterns in a DRAM device. The result shows that this EDA tool can handle the CD measurement data easily and can save us a lot of time and labor for the analysis. The procedures of systematic defect filtering and data handling using an EDA tool are presented in detail

Scanner matching using pupil intensity control between scanners in 30nm DRAM device

Scanner mismatch has become one of the critical issues in high volume memory production. There are several components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more critical in electrical performance and process window. In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices. We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer metrology data and scanner specific parameters are used to build a computational model, and determine the optimal settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and measured process window changes by applying the matching sub-recipe are also evaluated.

The APC (Advanced Process Control) procedure for process window and CDU improvement using DBMs

The downscaling of the feature size and pitches of the semi-conductor device requires enough process window and good CDU of exposure field for improvement of device characteristics and high yield. Recently several DBMs (Design Based Metrologies) are introduced for the wafer verification and feed back to for DFM and process control. The major applications of DBM are OPC feed back, process window qualification and advanced process control feed back. With these tools, since the applied tool in this procedure uses e-beam scan method with database of design layout like other ones, more precise and quick verification can be done. In this work the process window qualification procedure will be discussed in connection with EDA simulation results and then method for obtaining good CDU will be introduced. DoseMapperTM application has been introduced for better field CDU control, but it is difficult to fully correct large field with limited data from normal CD SEM methodology. New DBM has strong points in collecting lots of data required for large field correction with good repeatability (Intra / Inter field).

Application of DBM tool for detection of EUV mask defect

Extreme ultraviolet lithography (EUVL) is one of the most leading lithography technologies for high volume manufacturing. The EUVL is based on reflective optic system therefore critical patterning issues are arisen from the surface of photomask. Defects below and inside of the multilayer or absorber of EUV photomask is one of the most critical issues to implement EUV lithography in mass production. It is very important to pick out and repair printable mask defects. Unfortunately, however, infrastructure for securing the defect free photomask such as inspection tool is still under development furthermore it does not seem to be ready soon. In order to overcome the lack of infrastructures for EUV mask inspection, we will discuss an alternative methodology which is based on wafer inspection results using DBM (Design Based Metrology) tool. It is very challenging for metrology to quantify real mask defect from wafer inspection result since various sources are possible contributor. One of them is random defect comes from poor CD uniformity. It is probable that those random defects are majority of a defect list including real mask defects. It is obvious that CD uniformity should be considered to pick out only a real mask defect. In this paper, the methodology to determine real mask defect from the wafer inspection results will be discussed. Experiments are carried out on contact layer and on metal layer using mask defect inspection tool, Teron(KLA6xx) and DBM (Design Based Metrology) tool, NGR2170™.

Simple method for decreasing wafer topography effect for implant mask

Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implant layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build. In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.

Advanced overlay analysis through design based metrology

As design rule shrink, overlay has been critical factor for semiconductor manufacturing. However, the overlay error which is determined by a conventional measurement with an overlay mark based on IBO and DBO often does not represent the physical placement error in the cell area. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion caused by etching or CMP also can be a source of the mismatch. In 2014, we have demonstrated that method of overlay measurement in the cell area by using DBM (Design Based Metrology) tool has more accurate overlay value than conventional method by using an overlay mark. We have verified the reproducibility by measuring repeatable patterns in the cell area, and also demonstrated the reliability by comparing with CD-SEM data. We have focused overlay mismatching between overlay mark and cell area until now, further more we have concerned with the cell area having different pattern density and etch loading. There appears a phenomenon which has different overlay values on the cells with diverse patterning environment. In this paper, the overlay error was investigated from cell edge to center. For this experiment, we have verified several critical layers in DRAM by using improved(Better resolution and speed) DBM tool, NGR3520.

Real cell overlay measurement through design based metrology

Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties, several innovative resolution enhancement technologies, based on 193nm wavelength, were introduced and implemented to keep the trend of device scaling. Scanner makers keep developing state-of-the-art exposure system which guarantees higher productivity and meets a more aggressive overlay specification. “The scaling reduction of the overlay error has been a simple matter of the capability of exposure tools. However, it is clear that the scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieve the desired performance.(2)” In a manufacturing fab, the overlay error, determined by a conventional overlay measurement: by using an overlay mark based on IBO and DBO, often does not represent the physical placement error in the cell area of a memory device. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion, caused by etching or CMP, also can be a source of the mismatch. Therefore, the requirement of a direct overlay measurement in the cell pattern gradually increases in the manufacturing field, and also in the development level. In order to overcome the mismatch between conventional overlay measurement and the real placement error of layer to layer in the cell area of a memory device, we suggest an alternative overlay measurement method utilizing by design, based metrology tool. A basic concept of this method is shown in figure1. A CD-SEM measurement of the overlay error between layer 1 and 2 could be the ideal method but it takes too long time to extract a lot of data from wafer level. An E-beam based DBM tool provides high speed to cover the whole wafer with high repeatability. It is enabled by using the design as a reference for overlay measurement and a high speed scan system. In this paper, we have demonstrated that direct overlay measurement in the cell area can distinguish the mismatch exactly, instead of using overlay mark. This experiment was carried out for several critical layer in DRAM and Flash memory, using DBM(Design Based Metrology) tool, NGR2170™.

Systematic and random defects control with design-based metrology

As technology node of memory devices is approaching around 30nm, the process window is becoming much narrower and production yield is getting more sensitive to tiny defects which used to be not, if ever, so critical. So it would be very hard to expect the same production yield as now in near future. It is possible to classify wafer defects into systematic and random defects. Systematic defects can be also divided into design related and process related defects. Narrow process window, generally, is thought to be the source of these systematic defects and we have to extend process window with Design for Manufacturing (DFM) and control process variation with Advanced Process Control (APC) to ensure the production yield. The sensitivity of random defects, however, has something to do with the smaller design rule itself. For example, the narrower spaces between lines are subject to bridge defects and the smaller lines, to pinch defects. Die to data base (DB) Design Based Metrology (DBM) has mainly been in use for detecting systematic defects and feedback to DFM and APC so far. We are trying to extend the application of DBM to random defects control. The conventional defect inspection systems are reaching its highest limit due to the low signal to noise ratio for extremely small feature sizes of below 40nm. It is found that Die to DB metrology tool is capable of detecting small but critical defects with reliability.