Taehyeong Lee

Wide applications of design based metrology with tool integration

Recently several DBMs(Design Based Metrologies) are introduced for the wafer verification and feed back to DFM. The major applications of DBM are OPC accuracy feed back, process window qualification and advanced process control feed back. In general, however, DBM brings out huge amount of measurement data and it is necessary to provide special server system for uploading and handling the raw data. And since it also takes much time and labor to analyze the raw data for valuable feed back, it is desirable to connect to EDA tools such as OPC tools or MBV(Model Based Verification) tools for data analysis. If they can communicate with a common language between them, the DBM measurement result can be sent back to OPC or MBV tools for better model calibration. For advanced process control of wafer CDU, DBM measurement results of field CDU can be fed back to scanner for illumination uniformity correction. In this work, we discuss tool integration of DBM with other tools like EDA tools. These tool integrations are targeted for the verification procedure automation and as a result for faster and more exact analysis of measurement data. The procedures of tool integration and automatic data conversion between them will be presented in detail.

Application of DBM system to overlay verification and wiggling quantification for advanced process

With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges in process control. As lithography and etch processes are pushed to get smaller dimensions, the overlay and wiggling control are hot issues due to the limiting of pattern performance. Many chip makers are using Double Patterning Technology (DPT) process to overcome design rule limitations but they are also concerned about overlay control. In DPT process, obtaining accurate overlay data by measuring overlay marks with traditional metrology is difficult because of the difference of shape and position between cell pattern and overlay marks. Cell to overlay mark miss-match will occur when there is lens aberration or mask registration error. Therefore, the best way to obtain accurate overlay data without error is to measure the real cell itself. The overlay of the cell array using DPT process can be measured by analyzing the relative position of the 2nd exposed pattern to the 1st exposed pattern. But it is not easy to clearly distinguish a 1st layer and 2nd layer in a patterned cell array image using CD SEM. The Design Based Metrology (DBM)-system can help identify which cell pattern is a 1st or 2nd layer, so overlay error between the 1st and 2nd layers at DPT process can be checked clearly. Another noticeable problem in advanced processing is wiggling. The wiggling of a pattern become severe by the etch process and must be controlled to meet electrical characteristics of what the semiconductor device requires. The 1st stage of wiggling control is to understand the level of wiggling which is crucial to device performance. The DBM-system also can be used for quantification of wiggling by determining specially designed parameters. In this paper we introduce overlay verification and wiggling quantification through new methodology for advanced memory devices.

OPC verification and hotspot management for yield enhancement through layout analysis

As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and applied to lithography field. And we have struggled not only to obtain sufficient process window with those techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot management. Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip. Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this paper, new verification methodology based on design based analysis will be introduced as an alternative method for effective control of OPC accuracy and hot spot management.

Systematic defect filtering and data analysis methodology for design based metrology

Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The major applications of DBM are OPC accuracy improvement, DFM feed-back through Process Window Qualification (PWQ) and advanced process control. In general, however, the amount of output data from DBM is normally so large that it is very hard to handle the data for valuable feed-back. In case of PWQ, more than thousands of hot spots are detected on a single chip at the edge of process window. So, it takes much time and labor to review and analyze all the hot spots detected at PWQ. Design-related systematic defects, however, will be found repeatedly and if they can be classified into groups, it would be possible to save a lot of time for the analysis. We have demonstrated an EDA tool which can handle the large amount of output data from DBM by reducing pattern defects to groups. It can classify millions of patterns into less than thousands of pattern groups. It has been evaluated on the analysis of PWQ of metal layer in NAND Flash memory device and random contact hole patterns in a DRAM device. The result shows that this EDA tool can handle the CD measurement data easily and can save us a lot of time and labor for the analysis. The procedures of systematic defect filtering and data handling using an EDA tool are presented in detail

The APC (Advanced Process Control) procedure for process window and CDU improvement using DBMs

The downscaling of the feature size and pitches of the semi-conductor device requires enough process window and good CDU of exposure field for improvement of device characteristics and high yield. Recently several DBMs (Design Based Metrologies) are introduced for the wafer verification and feed back to for DFM and process control. The major applications of DBM are OPC feed back, process window qualification and advanced process control feed back. With these tools, since the applied tool in this procedure uses e-beam scan method with database of design layout like other ones, more precise and quick verification can be done. In this work the process window qualification procedure will be discussed in connection with EDA simulation results and then method for obtaining good CDU will be introduced. DoseMapperTM application has been introduced for better field CDU control, but it is difficult to fully correct large field with limited data from normal CD SEM methodology. New DBM has strong points in collecting lots of data required for large field correction with good repeatability (Intra / Inter field).

Application of DBM tool for detection of EUV mask defect

Extreme ultraviolet lithography (EUVL) is one of the most leading lithography technologies for high volume manufacturing. The EUVL is based on reflective optic system therefore critical patterning issues are arisen from the surface of photomask. Defects below and inside of the multilayer or absorber of EUV photomask is one of the most critical issues to implement EUV lithography in mass production. It is very important to pick out and repair printable mask defects. Unfortunately, however, infrastructure for securing the defect free photomask such as inspection tool is still under development furthermore it does not seem to be ready soon. In order to overcome the lack of infrastructures for EUV mask inspection, we will discuss an alternative methodology which is based on wafer inspection results using DBM (Design Based Metrology) tool. It is very challenging for metrology to quantify real mask defect from wafer inspection result since various sources are possible contributor. One of them is random defect comes from poor CD uniformity. It is probable that those random defects are majority of a defect list including real mask defects. It is obvious that CD uniformity should be considered to pick out only a real mask defect. In this paper, the methodology to determine real mask defect from the wafer inspection results will be discussed. Experiments are carried out on contact layer and on metal layer using mask defect inspection tool, Teron(KLA6xx) and DBM (Design Based Metrology) tool, NGR2170™.

Simple method for decreasing wafer topography effect for implant mask

Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implant layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build. In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.

Real cell overlay measurement through design based metrology

Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties, several innovative resolution enhancement technologies, based on 193nm wavelength, were introduced and implemented to keep the trend of device scaling. Scanner makers keep developing state-of-the-art exposure system which guarantees higher productivity and meets a more aggressive overlay specification. “The scaling reduction of the overlay error has been a simple matter of the capability of exposure tools. However, it is clear that the scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieve the desired performance.(2)” In a manufacturing fab, the overlay error, determined by a conventional overlay measurement: by using an overlay mark based on IBO and DBO, often does not represent the physical placement error in the cell area of a memory device. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion, caused by etching or CMP, also can be a source of the mismatch. Therefore, the requirement of a direct overlay measurement in the cell pattern gradually increases in the manufacturing field, and also in the development level. In order to overcome the mismatch between conventional overlay measurement and the real placement error of layer to layer in the cell area of a memory device, we suggest an alternative overlay measurement method utilizing by design, based metrology tool. A basic concept of this method is shown in figure1. A CD-SEM measurement of the overlay error between layer 1 and 2 could be the ideal method but it takes too long time to extract a lot of data from wafer level. An E-beam based DBM tool provides high speed to cover the whole wafer with high repeatability. It is enabled by using the design as a reference for overlay measurement and a high speed scan system. In this paper, we have demonstrated that direct overlay measurement in the cell area can distinguish the mismatch exactly, instead of using overlay mark. This experiment was carried out for several critical layer in DRAM and Flash memory, using DBM(Design Based Metrology) tool, NGR2170™.

Mask compensation for process flare in 193nm very low k1 lithography

Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.

Overlay metrology for low-k 1 : challenges and solutions

Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer exposures are presented which investigate various aspects of overlay metrology and validate our simulations.