H. Hashiguchi

New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of <; 1 μm. The electrostatic multichip temporary bonding technique enabled stress-free direct bonding of self-assembled chips. We obtained good electrical characteristics from 3D stacked chips fabricated by HSA-CtW using Cu/SnAg microbumps and Cu-TSVs.

Temporary spin-on glass bonding technologies for via-last/backside-via 3D integration using multichip self-assembly

In this study, we proposed and demonstrated self-assembly-based via-last/backside-via 3D integration using a temporary spin-on glass (SOG) bonding technology. A hydrogenated amorphous silicon (a-Si:H) was employed as a debonding layer. Known good dies (KGDs) were precisely self-assembled right side up on an electrostatic carrier wafer by surface tension of water, and then, the KGDs were fixed by applying DC voltage to the carrier. After that, the KGDs were temporarily bonded and transferred to another support glass wafer on which the a-Si:H and SOG layers were deposited. After multichip thinning, Cu-TSVs were formed on the KGDs. The resulting TSV daisy chains showed good electrical characteristics. The KGDs can be debonded with a 308-nm laser and transferred again to target interposer wafers.

Plasma assisted multichip-to-wafer direct bonding technology for self-assembly based 3D integration

We demonstrated plasma-assisted multichip-to-wafer direct bonding for self-assembly based 3D integration processes. We mainly evaluated the bonding yields and bonding strengths of dies obtained by multichip-to-wafer direct oxide-oxide bonding, and compared with wafer-to-wafer direct oxide-oxide bonding in their bonding properties. In this study, we employed thermal oxide and chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate (TEOS) as bonding interfaces, and in addition, N2 or Ar plasmas were used for the surface activation. We finally introduce multichip-to-wafer direct oxide-oxide bonding between self-assembled dies and wafers having the PECVD-oxide layer.

A new temporary bonding technology with spin-on glass and hydrogenated amorphous Si for 3D LSIs

A new temporary bonding technology has been demonstrated, where both spin-on glass (SOG) and hydrogenated amorphous silicon (a-Si:H) were used as a bonding layer and as a debonding layer, respectively. Square chips were bonded to a glass wafer through the SOG layer and a-Si:H layer. The SOG bonding was capable of withstanding chip thinning and high-temperature chemical vapor deposition (CVD) processes. A XeCl excimer laser was irradiated to the a-Si:H layer through the glass wafers for debonding the chips. A novel via-last/backside-via 3D integration process using temporary SOG bonding was also proposed for advanced multichip-to-wafer 3D integration with self-assembly.

3D Integration technologies using self-assembly and electrostatic temporary multichip bonding

We developed a new chip-to-wafer 3D integration technology using self-assembly and electrostatic (SAE) bonding. High-throughput multichip self-assembly with a high alignment accuracy within 1 μm was achieved by the SAE bonding technique. Self-assembled known good dies (KGDs) were temporarily bonded on SAE carriers by electrostatic bonding force. We implemented multichip transfer processes twice and then formed through-silicon vias (TSVs) for the self-assembled KGDs to fabricate 3D-stacked chips with Cu-TSVs and Cu/SnAg microbumps. By using the new multichip-to-wafer 3D integration process with SAE bonding, we obtained good electrical characteristics from the self-assembled KGDs having Cu-TSVs and Cu/SnAg microbumps.

Transfer and Non-transfer 3D Stacking Technologies Based on Multichip-to-Wafer Self-Assembly and Direct Bonding

Non-transfer and transfer based 3D integration technologies are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Both the stacking approaches employ KGD self-assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-treated plasma-TEOS SiO2 on their top surface are directly self-assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.

Highly thermoresistant temporary bonding/debonding system without organic adhesives for 3D integration

This study introduces a highly thermoresistant temporary bonding/debonding system. Known Good Dies (KGDs) were bonded through SOG to a support wafer. The KGDs were thinned, and Cu-TSVs were formed by via-last/backside-via processes. These KGDs can be readily debonded from the wafer by excimer laser irradiation to the a-Si:H layer on the wafer.

Investigation of the Plasma Damage by Etching Process for TSV Formation in Via-last Backside-via 3D IC

We have investigated the effect of plasma damage in TSV formation on MOSFET characteristics to discuss the new antenna rule for the 3D IC design. An IC chip for evaluation was bonded to Si interposer with Cu/Sn microbumps at 280°C for 190 sec and thinned to 50-m thickness. Via holes through a Si substrate for TSV are formed by ICP-RIE at the backside surface of the IC chip. Diameter and number of via holes are 25 m and 1, 6, 11, and 21, respectively. These via holes interconnected the first metal which interconnect the gate metal of MOSFET fabricated on IC chip. We measured the Id-Vg characteristics of the MOSFET before and after via-holes formation. The measurement results show no significant change even after via-holes formation. It is indicated that the via-hole-etching process doesn’t affect MOSFET characteristics, because the gate capacitance of MOSFET is much smaller than parasitic capacitance of the first metal.