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Dive into the research topics where H. Jaouen is active.

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Featured researches published by H. Jaouen.


IEEE Transactions on Electron Devices | 2005

A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET

E. Fuchs; Philippe Dollfus; G. Le Carval; Sylvain Barraud; D. Villanueva; F. Salvetti; H. Jaouen; T. Skotnicki

A backscattering model suitable for compact modeling of nanoscale MOSFET is developed within the Landauer flux-scattering theory. To describe the quasi-ballistic transport, a new backscattering model based on the accurate determination of ballistic and backscattering probabilities along the channel is developed. This model is based on a careful analysis of transport in device using Monte Carlo simulation. This model allows us to display the main physical quantities along the channel and to accurately describe the quasi-ballistic transport and its effects on current-voltage characteristics.


Applied Physics Letters | 2005

Combined synchrotron x-ray diffraction and wafer curvature measurements during Ni–Si reactive film formation

Christian Rivero; Patrice Gergaud; M. Gailhanou; O. Thomas; Benoit Froment; H. Jaouen; V. Carron

Combined x-ray diffraction and wafer curvature measurements during annealing of Ni thin films (13 nm) deposited on Si (001) reveal distinct stages in stress development and silicide growth. Thanks to this unique experimental setup, a clear correlation is established between force extrema at distinct temperatures and the appearance of new silicides. It is shown that the transient formation of Ni3Si2 has a strong influence on the overall stress development.


european solid state device research conference | 2005

LDMOS modeling for analog and RF circuit design

A. Canepari; Guillaume Bertrand; A. Giry; M. Minondo; F. Blanchet; H. Jaouen; B. Reynard; N. Jourdan; J.-P. Chante

This paper presents a complete SPICE sub-circuit model for a lateral double diffused N-MOS (NLDMOS) in a 0.25 m BICMOS technology. The proposed model accurately simulates single and multifinger devices up to geometry sizes used in the final application. The model is validated in DC, AC and large signal conditions. It accounts for all basic LDMOS phenomena such as graded channel, quasi-saturation and self-heating effects. Such study demonstrates that this sub-circuit approach can compete with recent physically based published compact models and even surpass them in terms of flexibility and portability in numerous simulators.


IEEE Transactions on Electron Devices | 2012

Modeling Stressed MOS Oxides Using a Multiphonon-Assisted Quantum Approach—Part II: Transient Effects

Davide Garetto; Yoann Mamy Randriamihaja; D. Rideau; Alban Zaka; Alexandre Schmid; Yusuf Leblebici; H. Jaouen

Multifrequency charge pumping analysis has been performed using a multiphonon-assisted charge trapping model in the view of analyzing the oxide region in energy and position that can be characterized using charge pumping (CP) characterization. Transient phenomena observed during CP and ac characterization (hysteresis loops) have been modeled, and the role of out-of-equilibrium quasi-Fermi levels in proximity of the Si/SiO2 interface has been studied in detail.


Microelectronics Reliability | 2007

FEM-based method to determine mechanical stress evolution during process flow in microelectronics, application to stress–voiding

S. Orain; J.-C. Barbé; X. Federspiel; P. Legallo; H. Jaouen

Mechanical stress is a major concern in microelectronics: the reliability of VLSI interconnects is mainly controlled by the stress levels. The increasing complexity of processes and the shrinking of feature sizes make it necessary to use quantitative modelling in order to optimise process parameters and device geometries. We had developed a method based on the use of some finite element analysis (FEA) tools, to quantitatively determine the stress evolution along the process flow. This method allows us to simulate material deposition, etching and thermal ramping steps. It was used to monitor the stress level in two metallic levels interconnected by a via during the fabrication. Our numerical results were analysed regarding the so-called stress-voiding phenomenon: these results allow us to point out the critical interface to focus on. All the obtained results are in good agreement with experimental observations. This method can be used to determine the evolution of the most probable void position as the geometry varies and then to optimise both the geometry and the process to minimize stress-induced voiding.


international workshop on computational electronics | 2010

Small signal analysis of electrically-stressed oxides with Poisson-Schroedinger based multiphonon capture model

Davide Garetto; Yoann Mamy Randriamihaja; D. Rideau; Erwan Dornel; F. Clark William; Alexandre Schmid; V. Huard; H. Jaouen; Yusuf Leblebici

Defects in MOSFET oxides are a major issue in CMOS technologies, affecting not only the device electrical performances but also compromising reliability and endurance. Using Charge-Pumping and C-V measurements, defects have been characterized in native and electrically-aged oxides. These electrical measurements have been compared to the predictions of advanced simulations, accounting for multi-phonon assisted emission/capture rates and including the presence of multiple defects and the contribution of electron and holes tunneling from both the gate and the channel. The proposed model allows an accurate description of the dynamics of trap occupation during electrical stress and can be used for the rigorous extraction of trap concentration from CV measurements.


international electron devices meeting | 2003

Impact of the lateral source/drain abruptness on MOSFET characteristics and transport properties

D. Villanueva; A. Pouydebasque; E. Robilliart; T. Skotnicki; E. Fuchs; H. Jaouen

The impact of the lateral doping abruptness (LA) of the source/drain extension still remains a polemic issue in CMOS transistor engineering. Based on dedicated simulations, it is shown that the maximum gain in on current achieved with steep profiles does not exceed 3%. Moreover, a suited analytical modeling indicates that the influence of the LA mostly resides in changing the effective channel length (Leff). Subsequently, the impact of the gate overlap is critically reviewed and actually appears to be mostly related to the analytical definition of the simulated device. Eventually, relying on a clear physical background, the analysis is carried out further to investigate the modulation of source injection properties in the framework of the backscattering theory and Monte Carlo (MC) simulations. We propose an additional injection effect that emerges at the source end potential barrier when the junction becomes very abrupt. This effect incorporated within the theory of Lundstrom enables further interpretation and understanding of the MC on-state current calculations.


IEEE Transactions on Electron Devices | 2012

An Efficient Nonlocal Hot Electron Model Accounting for Electron–Electron Scattering

Alban Zaka; Pierpaolo Palestri; Quentin Rafhay; R. Clerc; Matteo Iellina; D. Rideau; C. Tavernier; G. Pananakakis; H. Jaouen; L. Selmi

This paper presents a nonlocal model for channel hot electron injection in MOSFETs and nonvolatile memories, which includes a full-band description of optical phonon scattering rates and carrier group velocity. By virtue of its efficient formalism, this model can also include carrier-carrier scattering, which has a marked impact on gate current at low gate voltages. The model is compared against full-band Monte Carlo simulations of typical nor flash devices in terms of distribution functions, bulk current, gate current, and gate current density along the channel. A very good agreement is obtained for various drain and gate voltages and channel lengths.


international conference on simulation of semiconductor processes and devices | 2006

Low-Field Mobility in Strained Silicon with `Full Band' Monte Carlo Simulation using k.p and EPM Bandstructure

M. Feraille; D. Rideau; Andrea Ghetti; A. Poncet; C. Tavernier; H. Jaouen

Recent works have shown that accurate band-structure for strained silicon can be obtained using full-zone k.p method, In this paper we have performed full-band Monte Carlo transport simulations in strained silicon using k.p band structure, and we have compared to simulations performed using the well-benchmarked EPM band structure


international electron devices meeting | 2013

Mobility in high-K metal gate UTBB-FDSOI devices: From NEGF to TCAD perspectives

D. Rideau; Y. M. Niquet; Olivier Nier; A. Cros; Jean-Philippe Manceau; Pierpaolo Palestri; David Esseni; V. H. Nguyen; François Triozon; Jean Charles C Barbé; I. Duchemin; D. Garetto; Lee Smith; Luca Silvestri; Franck Nallet; R. Clerc; O. Weber; F. Andrieu; E. Josse; C. Tavernier; H. Jaouen

This paper aims to review important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. A simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools is presented.

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Yusuf Leblebici

École Polytechnique Fédérale de Lausanne

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