C. Tavernier

Impact of technology scaling in SOI back-channel total dose tolerance. A 2-D numerical study using self-consistent oxide code

A new 2D-self-consistent code has been developed and is applied to the understanding of charge trapping in SOI buried oxides and its effect on back-channel MOS leakage in SOI transistors. 2D effects, field-collapse and field-enhancement are observed. Clear indications on scaling trends are obtained with respect to supply voltage and oxide thickness. In thinner oxides, 2D effects are observed for example, the onset of back-channel leakage current is found to be related to the ratio of the channel length on the oxide thickness.

An atomistic investigation of the impact of in-plane uniaxial stress during solid phase epitaxial regrowth

We propose an atomistic comprehensive model based on a lattice kinetic Monte Carlo approach to analyse the impact of in-plane uniaxial stress during solid phase epitaxial regrowth. We observed no influence of tensile stress on the regrowth kinetics. In contrast, compressive stress leads to (i) a reduction of the macroscopic regrowth velocity, (ii) an enhancement of the amorphous/crystalline interface roughness, and (iii) defective Si formation. Our observations are in good agreement with experimental data from the literature. Our atomistic approach also clarifies the interpretation of the interface morphological instability based on the kinetics of microscopic events.

Evaluation and modeling of lanthanum diffusion in TiN/La2O3/HfSiON/SiO2/Si high-k stacks

In this study, TiN/La2O3/HfSiON/SiO2/Si gate stacks with thick high-k (HK) and thick pedestal oxide were used. Samples were annealed at different temperatures and times in order to characterize in detail the interaction mechanisms between La and the gate stack layers. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) measurements performed on these samples show a time diffusion saturation of La in the high-k insulator, indicating an La front immobilization due to LaSiO formation at the high-k/interfacial layer. Based on the SIMS data, a technology computer aided design (TCAD) diffusion model including La time diffusion saturation effect was developed.

Modeling of the effect of the buried Si–SiO2 interface on transient enhanced boron diffusion in silicon on insulator

The effect of the buried Si–SiO2 interface on the transient enhanced diffusion (TED) of boron in silicon on insulator (SOI) structures has been investigated. To this purpose, boron marker layers were grown by chemical vapor deposition on Si and SOI substrates and implanted under nonamorphizing conditions with 40 keV Si+ ions. The experimental results clearly confirm that the Si–SiO2 interface is an efficient trap for the Si interstitial atoms diffusing out of the defect region. Based on these experiments, existing models for the simulation of B TED in silicon have been modified to include an additional buried recombination site for silicon interstitials. The simulation results provide an upper limit of ∼5 nm for the recombination length of interstitials at the Si–SiO2 interface.

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

This paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded in situ sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded in situ sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness.

An Efficient Nonlocal Hot Electron Model Accounting for Electron–Electron Scattering

This paper presents a nonlocal model for channel hot electron injection in MOSFETs and nonvolatile memories, which includes a full-band description of optical phonon scattering rates and carrier group velocity. By virtue of its efficient formalism, this model can also include carrier-carrier scattering, which has a marked impact on gate current at low gate voltages. The model is compared against full-band Monte Carlo simulations of typical nor flash devices in terms of distribution functions, bulk current, gate current, and gate current density along the channel. A very good agreement is obtained for various drain and gate voltages and channel lengths.

Low-Field Mobility in Strained Silicon with `Full Band' Monte Carlo Simulation using k.p and EPM Bandstructure

Recent works have shown that accurate band-structure for strained silicon can be obtained using full-zone k.p method, In this paper we have performed full-band Monte Carlo transport simulations in strained silicon using k.p band structure, and we have compared to simulations performed using the well-benchmarked EPM band structure

Mobility in high-K metal gate UTBB-FDSOI devices: From NEGF to TCAD perspectives

This paper aims to review important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. A simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools is presented.

Modeling study of the SiGe/Si heterostructure in FDSOI pMOSFETs

We investigate an efficient way to handle the SiGe/Si heterostructure in pMOS FDSOI devices. The electrostatic is studied using a self consistent 6-band k.p Schrodinger-Poisson solver. We show that the heterostructure can be efficiently treated using an analytical in-plane integration of the charge density based on the effective mass approximation dispersion relation. The shift of the threshold voltage for various SiGe FDSOI pMOS structures with varying Ge content and strained SiGe layer thickness is shown.

Electromigration induced failure mechanism: Multiphysics model and correlation with experiments

In advanced semiconductor devices, most of the reliability issues in interconnect occurs at a very local scale, especially voiding phenomenon in copper lines induced by electromigration. Hence, a better understanding of mechanism governing electromigration is needed for developing more accurate lifetime models. In this paper, finite element simulations are carried out in that frame. Firstly, a model of vacancy migration is proposed. Thermal, stress and concentration gradients, and electrical current driven forces are considered. A realistic configuration of electromigration in a small segment of copper line is studied. The local vacancy accumulation at the cathode is observed. Distinct diffusion paths (lattice, grain boundary and interface) are implemented in a (111) oriented copper grains; it provide more realistic vacancy kinetics and it highlight large heterogeneity of concentration, which is responsible for void nucleation. Secondly, a model of void evolution, coupled with the transport vacancy model is implemented. To distinguish both metal and void phases, an order parameter field is introduced. The motion of the diffuse interface metal/void is solved by mean of the so-called level set method. The normal velocity of the front is directly computed thanks to the local vacancy concentration. Finally, the evolution of the line resistance in function of time and the void shape is output and analyzed. By facing simulation results with measurements and observations, a good agreement is revealed and efficiency of the implemented model is demonstrated.