H. Kimijima

Future perspective and scaling down roadmap for RF CMOS

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFETs are useful for future high-speed ULSI devices.

High performance RF characteristics of raised gate/source/drain CMOS with Co salicide

Summary form only given. In order to obtain high performance analog MOSFETs, it is important to reduce gate resistance. Recently W/Ti, CoSi/sub 2/ and NiSi gate electrodes have been proposed to realize these requirements. Especially, the Co salicided T-shape gate electrode realizes easily a low gate resistance below 1.5 ohm/sq. with a small increase in the number of process steps. Additionally, short channel effects are improved because the junction depth from the Si substrate surface at deeper source and drain regions becomes shallower due to the raised source and drain. In this paper, we demonstrate the excellent analog characteristics of Co salicided T-shape gate RF CMOS technology making use of a raised gate/source/drain structure. Extremely high fmax value of 70 GHz was realized by 0.10 /spl mu/m gate length nMOSFET with low noise and low power consumption.

A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime

Flicker noise characteristics of 1.5 nn direct-tunneling gate oxide n- and pMOSFETs have been investigated It was confirmed that in the shorter gate length region, less than 0.2 /spl mu/m, the flicker noise decreased with the decrease in gate oxide thickness even in the direct-tunneling regime. On the contrary, it was found that with gate length larger than 0.45 /spl mu/m, the flicker noise becomes larger than that of the thicker gate oxide MOSFETs due to large gate leakage current. The degradation of flicker noise after charge injection was also compared for MOSFETs with various gate oxide thickness.

0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology

We introduce a 0.12 /spl mu/m nMOS technology with multi-Vths for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 /spl mu/m nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.

On-chip spiral inductors with diffused shields using channel-stop implant

We investigated the Diffused shield Under the Oxide (DUO) for the first time. DUO is an extremely shallow diffusion layer in the n-well under the field oxide. DUO can be formed by high energy implantation through the field oxide, and it can be formed by the process of the channel stop implant for MOSFETs simultaneously. Application of DUO provided a 79% improvement in Q-factor and the comparable shield effect on the n-well. This structure is one of the suitable ground shield for the spiral inductor of the rf CMOS.

An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFETs with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm 2 ) and SRAM (0.195μm 2 ) for wide range of mobile applications with wireless system

Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin is also accomplished by minimizing random impurity fluctuation using Hf doped silicate as gate dielectrics. In addition, novel DFM (Design for Manufacturing) techniques are introduced for systematic yield improvement.

Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique

A non-doped selective epitaxial Si channel technique has been applied to ultra-thin gate oxide CMOS transistors with TiN and polysilicon gate electrodes, and its effect on direct-tunneling gate leakage current has been investigated. It was found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current in both the TiN and polysilicon gate electrode cases. Improved drain current drive and transconductance of the epitaxial channel MOSFETs with ultra-thin gate oxides in the direct-tunneling regime has been also demonstrated.

The Impact of Technology Scaling for RF Complementary Metal–Oxide–Semiconductor

Optimum methodology of scaling for RF complementary metal–oxide–semiconductor (CMOS) has been studied by investigating cutoff frequency ( fT), maximum oscillation frequency ( fmax), RF noise, and linearity with simulations and experiments. In the case of MOS field effect transistors (MOSFETs) with multi-finger structure, fmax and noise figure show trade-off between gate resistance and gate-bulk capacitance because of the existence of gate area for contact. By optimizing finger length for each technology, high fmax and low minimum noise figure are realized with little sacrifice of fT. In terms of the linearity, optimized gate width scaling is important. Stress enhancement technique is confirmed to be beneficial also in RF performance because of the enhancement of mobility which results in improvement of fT and other RF characteristics. It should be concluded that the improvement of RF characteristics is expected with scaling down the devices by adding gate width and finger length as the significant scaling parameters.