H. Klose

Micromechanics compatible with an 0.8 μm CMOS process

Results on a new approach for the monolithic integration of micromechanics and electronics are presented. The same process steps and layers can be used for both the mechanical and the electronic elements. This is a promising process concept for integrated microelectromechanical systems with a minimum of additional costs compared to the standard electronics process. Results on the fabrication of micromechanical structures using the process steps of a 0.8 μm CMOS process are given. The sublimation technique is used to dry the released surface-micromachined structures and different sublimating chemicals are compared. The influences of polycrystalline and amorphous deposition as well as diffusion doping and ion implantation on the strain gradients of the structural layers are presented. A fabricated electrostatically deflectable and capacitively detectable cantilever is presented and the dependence of the capacitance on the drive voltage is shown. By using the presented theory and fitting calculations to the measured non-linear characteristic, a value of 170 GPa for Youngs modulus of the polysilicon film is extracted.

Process-optimization for sub-30 ps BiCMOS technologies for mixed ECL/CMOS applications

The authors present a 0.8 mu m BiCMOS technology for high-performance digital applications. The underlying optimization strategy to trade off both bipolar vs. CMOS speed and cutoff-frequency vs. collector-emitter breakdown voltage is described. Based on this approach 23.5 GHz cutoff frequency and 28 ps CML gate-delay times could be obtained for the bipolar device, making this technology perfectly suited for mixed CMOS/ECL (emitter-coupled logic) types of applications. This is additionally proved by high-speed benchmark circuits such as 2:1 frequency dividers operating up to 13.5 GHz.<<ETX>>

Narrow BF/sub 2/ implanted bases for 35 GHz/24 ps high-speed Si bipolar technology

The authors report on a high-speed Si bipolar self-aligned technology featuring deep trench isolation for low capacitances, a production-compatible 15-keV BF/sub 2/ base implantation for high cutoff frequency, and an advanced composite material spacer formation process which avoids any etch removal of the base profile allowing for perfect control of the base charge. This process results in extremely reproducible device characteristics. The authors fabricated transistors with measured cutoff frequencies in excess of 35 GHz and realized CML ring oscillators which achieved a minimum delay time of 24 ps/gate. To check for degradation effects arising from residues of fluorine due to BF/sub 2/ implantation they processed reference transistors with B bases implanted at effectively identical energies as the BF/sub 2/ devices. With respect to base/emitter breakdown characteristics, no significant difference between the two sets of samples was observed. Thus, it is concluded that a 15 keV BF/sub 2/ implantation for narrow base formation is a viable approach for realizing bipolar devices for high-speed ICs.<<ETX>>

Modular deep trench isolation scheme for 38 GHz self-aligned double polysilicon bipolar devices

A modulator CMOS-compatible isolation scheme which is based on a deep trench technology combined with LOCOS is presented. In contrast to already established schemes, trench formation is postponed until after the LOCOS process. Thus thermal cycling is minimized. The high-performance potential of this isolation technology is demonstrated via fabrication of self-aligned double polysilicon transistors featuring a maximum cutoff frequency of 38 GHz.<<ETX>>

BICMOS - The Technology for Integrating Systems onto One Silicon IC

The objective of this paper is to provide a state of the art review on BICMOS technologies, their tradeoffs with respect to cost vs. performance and to outline the prospects of this technology. For this purpose, the fundamental properties of MOS and BIPOLAR are summarized, the basic technology items are discussed and the trade-off of cost vs. performance is done. Recent results are highlighted and future trends are sketched.

Low cost and high performance BiCMOS processes: a comparison

A modular 1.2- mu m BiCMOS process which can be used to realize either low-cost or high-performance bipolar devices within a CMOS environment is discussed. process complexity, electrical data, and circuit performance are compared for different circuit applications. It is shown that by the high-performance process mixed CMOS/ECL (emitter-coupled-logic) circuits with gate delays as low as 65 ps and data rates above 10 Gb/s can be realized.<<ETX>>

Heavy-doping transport parameter set describing consistently the DC and AC behavior of bipolar transistors

Using transistors with opaque polysilicon-emitters, the apparent bandgap narrowing in heavily doped n-type silicon has been measured with a temperature-dependent DC method. Collector currents and forward transit times of polysilicon-emitter transistors with different base doping levels in the heavy-doping region of N/sub A/>or=10/sup 17/ cm/sup -3/ have been determined. Comparing these measured values with simulated ones, different heavy doping parameter sets have been used for modeling. At N/sub D/=1.5*10/sup 20/ cm/sup -3/, the apparent bandgap narrowing is shown to amount to 105 meV. No existing heavy-doping parameter set is able to describe the DC as well as AC behavior of bipolar devices with heavily doped base layers. A new parameter set is suggested which correctly describes the DC and AC characteristics of these devices with a maximum uncertainty of about 30%.<<ETX>>

A 10 GHz High Performance BICMOS Technology for Mixed CMOS/ECL ICs

A 1.2 μm BICMOS process is presented for the realization of high complexity CMOS-circuits together with high performance bipolar transistors on the same chip. n+-/p-buried layers, a p-well CMOS-process and a double - polysilicon selfaligned bipolar process are the main technology features. A cut - off frequency of 10 GHz as well as a CML gat delay time of 65 ps are the results obtained with this process.

A 47 GHz bipolar process with an ultra shallow ion implanted base of 35 nm

Based on the bipolar process B6HF/1/l a scaled down version-further on denoted as B6HF*-was developed featuring 47 GHz cutoff-frequency for a 0.3 /spl mu/m effective emitter size transistor. To obtain this performance aggressive implantation and thermal budget strategies had been set up. The transistor base width has been reduced down to 35 nm, the lowest value ever reported for a conventional implanted base. Investigations with respect to process and device stability.<<ETX>>

Ultrashallow Emitter-Base Profiles by Double Diffusion

The diffusion of boron out of polysilicon was investigated. Diffusion and segregation coefficients were determined for furnace annealing and rapid thermal processing. Double polysilicon self-aligned npn bipolar transistors with sub 100 nm base widths were obtained, using the double diffusion technique. Calculations for the optimization of the base pinch resistance are presented. It is shown that base widths as low as 50 nm can be obtained with the double diffusion technique.