T.F. Meister

Process and device related scaling considerations for polysilicon emitter bipolar transistors

Vertical scaling of poly-Si emitter bipolar transistors is investigated based on experimental data and on one-dimensional device simulation. Emitter junction depths of 30 to 50 nm with excellent device characteristics are demonstrated and base widths around 50 nm are shown to be achievable on the basis of well proven processing techniques. It is shown that forward transit times around 3 ps corresponding to about 50 GHz transit frequency can be expected for such devices. An important result for these very shallow emitter base structures is that emitter and base charge storage contribute comparable amounts to the total forward transit time.

Vertical Scaling Considerations for Polysilicon-Emitter Bipolar Transistors

Until the early 1980s, the industrial standard of high-speed bipolar processes was characterized by implanted base and arsenic implanted, metal-contacted emitter devices. One of the essential achievements leading to the “renaissance” of bipolar technology [3.1] that has occurred since then is the use of polycrystalline silicon (poly-Si) as diffusion source and contact material for the emitter. Besides facilitating the second important achievement, self-alignment between emitter and base contact, the poly-Si emitter has the following major advantages: i.) Without compromising current gain, extremely shallow emitter junction depths can be formed, leading to a strong reduction in emitter charge storage. ii.) Due to the shallow emitter junction, extremely narrow base regions can be realized with sufficient process control. This, of course, serves to reduce base transit time. iii.) The polysilicon layer interposed between the active emitter region and the metal contact enhances device yield considerably due to its gettering capability and its blocking action against metal sintering and spiking .

The role of the interfacial layer in bipolar (poly-Si)-emitter transistors

Abstract Devices with and without an intentionally grown oxide at the poly/mono interface are investigated. By varying the thickness of the poly-Si layer the important role of the poly/mono interface in reducing the base current has been shown. Even in the case of “clean” interfaces the base current is independent of the thickness of the poly-Si layer. Devices with a thermally grown interfacial oxide (≈ 15 A) lead to degraded current characteristics and nonlinear emitter resistance. Describing the interface by a simple tunneling model, the barrier height and width both for minority and majority carriers are determined. This has been achieved by analysing the temperature behavior of both the emitter resistance and the effective recombination velocity of the poly/mono interface. The results are compared with HXTEM studies of the interface.

A 10 GHz High Performance BICMOS Technology for Mixed CMOS/ECL ICs

A 1.2 μm BICMOS process is presented for the realization of high complexity CMOS-circuits together with high performance bipolar transistors on the same chip. n+-/p-buried layers, a p-well CMOS-process and a double - polysilicon selfaligned bipolar process are the main technology features. A cut - off frequency of 10 GHz as well as a CML gat delay time of 65 ps are the results obtained with this process.

Base current analysis of poly-Si emitter bipolar transistors

Polysilicon emitter bipolar transistors with clear poly/mono-interfaces have been fabricated and base currents have been measured and analyzed in detail. The sources of base current within the pn-junction, the mono-Si part and the poly-Si part of the emitter are identified and separated. Measurements have been described and carried out precisely describing the recombination phenomena within the crystalline emitter. Currently used parameters as bandgap narrowing and Auger recombination are shown to be correct, whereas the electrically active doping within the polysilicon emitter is found to be drastically lower than within commonly processed emitters. Also the interface recombination velocity is much lower than that of directly metallized emitters. Both these results explain the substantial reduction of base current in polysilicon emitters, thus removing previously reported discrepancies between experiment and simulations. The effects of the mono-Si part on base current can be identified and separated out leaving an effective recombination velocity S as a figure of merit for the poly part of the emitter. This parameter S integrally describes recombination and transport phenomena within the poly-Si part of the emitter and the interface. The quantity S is based on experimental data only and necessary as well as sufficient to describe the effects of poly-Si on base current, without the necessity to get involved into the very complex details of transport within poly-Si layers and across grain boundaries. The dependence of S on processing conditions and implications for optimization of poly-Si emitter transistors are discussed.