K. Ehinger

Process and device related scaling considerations for polysilicon emitter bipolar transistors

Vertical scaling of poly-Si emitter bipolar transistors is investigated based on experimental data and on one-dimensional device simulation. Emitter junction depths of 30 to 50 nm with excellent device characteristics are demonstrated and base widths around 50 nm are shown to be achievable on the basis of well proven processing techniques. It is shown that forward transit times around 3 ps corresponding to about 50 GHz transit frequency can be expected for such devices. An important result for these very shallow emitter base structures is that emitter and base charge storage contribute comparable amounts to the total forward transit time.

Progress in speed power performance of bipolar technology by sub-10 keV B implantation into amorphized Si

Double polysilicon self-aligned bipolar n-p-n transistors have been fabricated with very narrow base widths by using very low-energy ion implantation of B at 2, 5, and (for comparison) 10 keV. To prevent channeling of B ions during implantation, several samples are amorphized by Ge ion implantation prior to the /sup 11/B implant. A two-step annealing cycle with minimum thermal budget is described which meets the requirements for defect-free recrystallization of the amorphous layer and the damaged region while simultaneously avoiding, as far as possible, diffusion broadening of the B profile. These optimal conditions result in transistors with cutoff frequencies up to 28 GHz (at V/sub CB/=3 V) and CML ring oscillators with 3.7-mW power consumption per gates at a minimum delay time of 35 ps/gate.<<ETX>>

Narrow BF/sub 2/ implanted bases for 35 GHz/24 ps high-speed Si bipolar technology

The authors report on a high-speed Si bipolar self-aligned technology featuring deep trench isolation for low capacitances, a production-compatible 15-keV BF/sub 2/ base implantation for high cutoff frequency, and an advanced composite material spacer formation process which avoids any etch removal of the base profile allowing for perfect control of the base charge. This process results in extremely reproducible device characteristics. The authors fabricated transistors with measured cutoff frequencies in excess of 35 GHz and realized CML ring oscillators which achieved a minimum delay time of 24 ps/gate. To check for degradation effects arising from residues of fluorine due to BF/sub 2/ implantation they processed reference transistors with B bases implanted at effectively identical energies as the BF/sub 2/ devices. With respect to base/emitter breakdown characteristics, no significant difference between the two sets of samples was observed. Thus, it is concluded that a 15 keV BF/sub 2/ implantation for narrow base formation is a viable approach for realizing bipolar devices for high-speed ICs.<<ETX>>

Modular deep trench isolation scheme for 38 GHz self-aligned double polysilicon bipolar devices

A modulator CMOS-compatible isolation scheme which is based on a deep trench technology combined with LOCOS is presented. In contrast to already established schemes, trench formation is postponed until after the LOCOS process. Thus thermal cycling is minimized. The high-performance potential of this isolation technology is demonstrated via fabrication of self-aligned double polysilicon transistors featuring a maximum cutoff frequency of 38 GHz.<<ETX>>

A Si-bipolar 23 Gbit/s multiplexer and a 15 GHz 2:1 static frequency divider

A 2:1 time-division multiplexer and a 2:1 static frequency divider with two separate outputs (phase difference 0 degrees and 90 degrees ) are presented. Both ICs are fabricated with a 1- mu m silicon bipolar self-aligning technology designed for a single supply voltage of 5 V. The maximum operating frequency of the static 2:1 frequency divider was found to be 15.7 GHz. The multiplexer has shown successful operation up to data rates as high as 23 Gb/s.<<ETX>>

Pedestal Collector in Advanced Bipolar Technology for Improved Speed Power Performance

A double poly-Si self-aligning bipolar process employing 1, μm lithography has been developed for very high speed/low power circuit applications. Shallow base-emitter profiles were obtained by combining low energy boron implantation and rapid thermal annealing for the emitter drive-in. Cut-off frequencies of 14 GHz at VBC = -1 V, ECL gate delay times of 43 ps and minimum power delay products of 30 fj were achieved with conventional epitaxial collector configurations. Further improvements in cut-off frequency up to 18 GHz, gate delay and minimum power delay product as low as 36 ps and 23 fJ, respectively, were attained by an additional implantation of doubly ionized phosphorus into the active device area forming a so-called pedestal collector.

Collector optimization for high-speed bipolar transistors

An efficient optimization procedure to improve the AC performance of integrated bipolar transistors is presented. Using the same emitter and base doping profiles, a reduction of the forward transit time T/sub f/ and thus a considerable improvement in the transit frequency f/sub T/ (more than 33% in the peak value) are achieved by optimizing the collector dopant profile. >

A 15 GHz 2:1 Static Frequency Divider in a 1μm Silicon Bipolar Technology

A 2:1 static frequency divider with two separate outputs shifted in phase to each other by 90° is presented. The IC is fabricated with a 1 μm silicon bipolar self-aligning technology designed for a single supply voltage of 5 V. The maximum operating frequency of the static 2:1 frequency divider was found to be 15.7 GHz with a power consumption of 245 mW. To the authors knowledge this is the highest value reported for a 2:1 static frequency divider in this configuration.