J. Hauenschild

A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology

A decision circuit and a 1:2 regenerating demultiplexer, which are key components in optical-fiber transmission links, were fabricated in an advanced self-aligning silicon bipolar technology using 0.8- mu m lithography. Maximum speed rather than low power consumption was the main goal of these designs. The transistors were individually optimized using a semiphysical transistor model for circuit simulation. At such high operating speeds the influence of the metal lines on the chip has to be taken into account. Worst-case conditions, caused, e.g., by fabrication spread and variation of the junction temperature, were met. The measured data rates of 22 Gb/s for the decision circuit and 32 Gb/s for the demultiplexer, with excellent retiming capability, have not yet been achieved with any semiconductor technology.<<ETX>>

A silicon bipolar decision circuit operating up to 15 Gb/s

A master-slave D-flip-flop (MS-D-FF) IC usable as a decision circuit has been realized in an advanced self-aligned silicon bipolar technology using 0.8- mu m lithography. The circuit has been operated up to 15 Gb/s (at a clock phase margin (CPM) of 180 degrees C) with a 5-V supply voltage. The data rate of 15 Gb/s is not the limit of this decision circuit if CPM values lower than 180 degrees can be tolerated, or if input voltage swings above 400 mV/sub p-p/ are available. >

A 15 GHz 2:1 Static Frequency Divider in a 1μm Silicon Bipolar Technology

A 2:1 static frequency divider with two separate outputs shifted in phase to each other by 90° is presented. The IC is fabricated with a 1 μm silicon bipolar self-aligning technology designed for a single supply voltage of 5 V. The maximum operating frequency of the static 2:1 frequency divider was found to be 15.7 GHz with a power consumption of 245 mW. To the authors knowledge this is the highest value reported for a 2:1 static frequency divider in this configuration.