A. Felder

42 GHz static frequency divider in a Si/SiGe bipolar technology

Frequency dividers are key components for multi-gigabit-per-second optical fiber links. For this application, maximum speed is mandatory, while the power consumption is not a limiting factor. To date, the highest operating speed for static frequency dividers has been achieved with III-V devices. For AlInAs/GaInAs HBTs with 130 GHz f/sub T/, 39.5 GHz operation is measured, and for 0.1 /spl mu/m InAlAs/InGaAs HEMTs with f/sub T/ of approximately 200 GHz an operating speed of 40.4 GHz is recently reported. The fastest published static silicon divider operates up to 35 GHz. Silicon bipolar technologies offer high reliability and cost-effectiveness. This divider is fabricated in a 0.5 /spl mu/m double-polysilicon self-aligned Si/SiGe heterojunction bipolar technology.

25 to 40 Gb/s Si ICs in selective epitaxial bipolar technology

High-speed digital ICs as decision circuits, time-division multiplexers (MUX), demultiplexers (DEMUX), and frequency dividers are key components for multigigabit-per-second optical-fiber links. While advanced silicon bipolar technology meets the demands for all electronic components of 10-Gb/s direct detection transmission links now in development, there is a question whether the situation will change at transmission rates of 20 Gb/s. The authors try to answer this question by presenting the above key components with record operating speeds. A silicon bipolar technology with selective epitaxial growth (SEG) of the active base and collector regions is used for circuit fabrication. A static 16:1 low-power frequency divider demonstrates the low-power capability of the SEG technology. All measured data rates and frequencies are significantly higher than reported values for silicon ICs and, with one exception, even for III-V ICs. The 40 Gb/s measured with the DEMUX is the highest data rate achieved with an IC in any technology.<<ETX>>

A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology

A decision circuit and a 1:2 regenerating demultiplexer, which are key components in optical-fiber transmission links, were fabricated in an advanced self-aligning silicon bipolar technology using 0.8- mu m lithography. Maximum speed rather than low power consumption was the main goal of these designs. The transistors were individually optimized using a semiphysical transistor model for circuit simulation. At such high operating speeds the influence of the metal lines on the chip has to be taken into account. Worst-case conditions, caused, e.g., by fabrication spread and variation of the junction temperature, were met. The measured data rates of 22 Gb/s for the decision circuit and 32 Gb/s for the demultiplexer, with excellent retiming capability, have not yet been achieved with any semiconductor technology.<<ETX>>

A 50 GHz implanted base silicon bipolar technology with 35 GHz static frequency divider

A 0.5 /spl mu/m silicon bipolar technology for mixed digital/analogue RF applications is presented. Very steep base profiles are realized by ion implantation and subsequent base diffusion. Cut-off frequencies and maximum oscillation frequencies of 50 GHz and ECL gate delay of 16 ps are obtained without increasing the process complexity in comparison to a 0.8 /spl mu/m production technology. A static 2:1 frequency divider operates up to 35 GHz, the highest value reported for any silicon based technology.

Static silicon frequency divider for low power consumption (4 mW, 10 GHz) and high-speed (160 mW, 19 GHz)

Two different static frequency dividers have been designed and fabricated in an advanced silicon self-aligning bipolar technology, demonstrating the high-speed and low-power capability of the technology. Maximum operating frequencies of 10.5 GHz and 19 GHz were measured at power dissipations of 4 mW and 160 mW, respectively, for the 2:1 dividing function. These results prove that silicon ICs may play an important role in communication systems in which extremely low power consumption is required at medium frequencies.<<ETX>>

40 Gb/s integrated clock and data recovery circuit in a silicon bipolar technology

An integrated clock and data recovery circuit (CDR) applying the PLL technique has been developed for future optical transmission systems. It is fabricated in a 0.5 /spl mu/m/50 GHz f/sub T/ double-polysilicon bipolar technology using only production-like process steps. The circuit operates up to 40 Gb/s, which is the highest operating speed to date for this type of IC in a silicon bipolar technology.

30 GHz static 2:1 frequency divider and 46 Gb/s multiplexer/demultiplexer ICs in a 0.6 /spl mu/m Si bipolar technology

High-speed digital functions realised as a 30 GHz static frequency divider and 46 Gb/s multiplexer and demultiplexer are presented. These ICs demonstrate the speed potential of silicon bipolar technology obtained by optimized combination of well-proven transistor concepts and production technology like process steps in a 0.6 /spl mu/m CMOS production environment. The measured results are record data not only for silicon but, except for the static divider, for all semiconductor technologies.

A Si-bipolar 23 Gbit/s multiplexer and a 15 GHz 2:1 static frequency divider

A 2:1 time-division multiplexer and a 2:1 static frequency divider with two separate outputs (phase difference 0 degrees and 90 degrees ) are presented. Both ICs are fabricated with a 1- mu m silicon bipolar self-aligning technology designed for a single supply voltage of 5 V. The maximum operating frequency of the static 2:1 frequency divider was found to be 15.7 GHz. The multiplexer has shown successful operation up to data rates as high as 23 Gb/s.<<ETX>>