H. Ohta

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.

High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD

Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported. We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure. Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE. Electron and hole mobility enhancement can be balanced by aggressively scaled poly-Si pMOS gate height and SiN capped shallow trench isolation (STI) with SiN liner. A high performance 30 nm/33 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 937/1000 muA/mum and 490/545 muA/mum at Vd=1.0 V / Ioff=100 nA/mum, respectively

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications

A 40 nm CMOS transistor, an ultra high density 6T SRAM cell, and 10-level Cu interconnects and very-low-k (VLK) dielectrics for high performance microprocessor applications are presented. Key process features are the following: (1) High-NA 193 nm photolithography with phase shift mask and optical proximity correction (OPC) allows 40 nm gate length and the smallest 6T SRAM cell (<1 /spl mu/m/sup 2/). (2) A unique transistor feature which is referred to as sidewall-notched gate enables an optimal pocket implant placement and suppresses variations of the notch width much better than poly-notched gate structure. (3) 1.1 nm nitrided oxide (1.9 nm inversion T/sub ox/) is used to achieve high drive current, and the thermal budget is reduced to suppress the boron penetration. (4) SiC-capped Cu/SiLK structure in 0.28 /spl mu/m pitch metal 1-4 layers realizes k/sub eff/ of 3.0.

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

A new powerful strain booster named as dopant confinement layer (DCL) technique is proposed for the first time. DCL technique is a novel stress memorization technique (SMT). Our proposed method doesnt require any additional capping layers used in SMT. DCL fabricated directly on the gate dielectric film effectively improved drive currents without degrading short channel immunity because DCL technique dose not affect halo, extension and source/drain (S/D) profiles. The higher dopant concentration in DCL resulted in both the better electron mobility and the thinner equivalent oxide thickness of inversion layer capacitance (Teff). Consequently, the higher drive currents of 1204 muA/mum and 786 muA/mum were obtained at Vdd=1.0 V for nMOSFET and pMOSFET, respectively.

Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology

We developed a novel junction profile engineering technique that uses laser spike annealing (LSA): LSA is implemented prior to spike-RTA to modulate the junction profile. With this technique, we can improve the performance of MOSFETs more effectively than conventional techniques. In addition, it enables us to use lower LSA temperatures with wide process window (at least 60degC) because of its low sensitivity to LSA temperatures within a certain range, while the conventional ways require ultra high temperatures to improve the device performance. We applied this technique to 45-nm node high performance (HP) CMOS devices with a gate length of 32-nm. A reduction in the source-drain parasitic resistance achieves 8.8% / 5% of improvements in the saturation on-current (Ion) for PMOS / NMOS, and Ion = 750(P) / 1030(N) [muA/mum] for Ioff = 100 [nA/mum] at Vdd= 1.0V. We also demonstrated the advantages of this technique by evaluating the performance of ring oscillators, SRAM yields and accuracy of precision poly resistors from the LSI manufacturing point of view.

High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

This paper demonstrates high performance 35 nm gate length CMOSFETs for 65 nm technology node. The impact of vertical gate scaling on dopant activation in poly-Si gate and device performance is investigated. Total stress controls form both STI and interconnect improved the nMOS drive current up to 5-10% without degradation for pMOS. Excellent controlled 35 nm gate length CMOSFETs are achieved with a high drive current of 650 uA/um for nMOS and 310 uA/um for pMOS at Ioff=70 nA/um at supply voltage of 0.85 V. Low CV/I values of 0.85 ps for nMOS and 1.61 ps for pMOS are obtained. These results are competitive among the latest published data.

Novel Thin Sidewall Structure for High Performance Bulk CMOS with Charge-Assisted Source-Drain-Extension

We have developed a novel junction profile engineering using thin sidewall structure and applied it to sub-40 nm uniaxial strained CMOS devices. This transistor used a high-k thin sidewall with electrical charge in achieving a higher drive current with keeping the short channel effect. Consequently, the 18.5/15.6% reduction of parasitic resistance achieve the 8.2/13.0% improvement in the saturation current (Ion) at 38 nm gate length for nMOS and pMOS. In addition, Ion dependence on active width (Wg) for pMOS is very small. In the size of active width : 0.1 mum, a 42% of Ion enhancement gave us Ion = 680 muA/mum at Vdd=1 V. These characteristics are originated from formation of inversion layer and suppressing channeling penetration of pocket impurities implanted. A high performance Bulk nMOS and pMOS were demonstrated with Ion of 1069 muA/mum and 725 muA/mum at Vdd=1 V / Ioff=100 nA/mum, respectively.

Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon

Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addition, we developed novel stack-SIN gate dielectrics by using bis-tertiarybutylamino-silane (BTBAS)/NH3. Novel stack-SIN gate dielectrics show higher immunity to negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime compared with conventional plasma nitrided silicon dioxide. These characteristic are originated from its unique nitrogen profile. The nitrogen concentration is over 22% at the surface of the dielectric and it rapidly decreases to 1% at the interface with a substrate. A high performance 30 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 1042 muA/mum and 602 muA/mum at Vd = 1 V / Ioff=100 nA/mum, respectively