Naoyoshi Tamura

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

The recent rapid spread of smart-phone use has resulted in a strong demand for a multi-band RF part with reduced size and power consumption. In the creation of an ideal RF system-on-a-chip, the biggest challenge is to realize a fully integrated PA in CMOS. In conventional PAs in compound semiconductor technologies, face-up wire-bond assembly with off-chip matching components is typically used, but flip-chip packaging is more suitable for slim mobile phones in which low-profile components are desired as well as for future integration with an RF transceiver in which the same packaging scheme is widely used. The PA for GSM [1] was insufficient for our target, so we needed to greatly improve the linearity in order to comply with the W-CDMA standard, which has better frequency-usage efficiency. Conventional CMOS PAs only support a single band [2,3] or are for WLAN [4] where the output power level is low (typically about 20dBm). In this paper, we present a fully-integrated triple-band linear CMOS PA for W-CDMA. Its flip-chip package is just 3.5×4×0.7mm3, and the average current consumption is less than 20mA.

High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD

Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported. We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure. Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE. Electron and hole mobility enhancement can be balanced by aggressively scaled poly-Si pMOS gate height and SiN capped shallow trench isolation (STI) with SiN liner. A high performance 30 nm/33 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 937/1000 muA/mum and 490/545 muA/mum at Vd=1.0 V / Ioff=100 nA/mum, respectively

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Aggressively scaled 25 nm gate CMOSFETs for the 65 nm node are reported. We successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc.). Both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration. High drive currents of 840/1010 /spl mu/A//spl mu/m and CV/I values of 0.54/0.60 psec with 25/33 nm gate nMOSFETs were achieved at Vdd=1 V and Ioff=100 nA//spl mu/m. They are the best values among recent published papers.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

Embedded silicon germanium (eSiGe) technologies for 45nm nodes and beyond

This paper reviews main technologies of embedded silicon germanium (eSiGe) for 45 nm node and beyond .There are three key techniques and an item to be considered carefully as follows. The first technique is a low temperature of epitaxial growth at 550degC to suppress stacking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Sigma)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface pre-cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. The final item to be considered carefully is boron concentration in eSiGe, because excessive boron compensates the strain in eSiGe as well as carbon. Finally We demonstrated the Ion = 0.795 mA/mum@Ioff = 100 nA/mum using above key techniques and an item.

Interface Roughness Produced by Nitrogen Atom Incorporation at a SiO2/Si(100) Interface

The critical amount of nitrogen atoms at the interface, above which the roughness of the oxynitride/Si(100) interface increases, was studied using noncontact-mode atomic force microscopy and X-ray photoelectron spectroscopy. The interface roughness was found to increase upon increasing the amount of nitrogen atoms at and near the interface if the amount of nitrogen atoms is greater than 0.37 monolayers. This increase in interface roughness was found to be reflected in an increase in surface roughness of almost the same amount.

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology

We developed a novel junction profile engineering technique that uses laser spike annealing (LSA): LSA is implemented prior to spike-RTA to modulate the junction profile. With this technique, we can improve the performance of MOSFETs more effectively than conventional techniques. In addition, it enables us to use lower LSA temperatures with wide process window (at least 60degC) because of its low sensitivity to LSA temperatures within a certain range, while the conventional ways require ultra high temperatures to improve the device performance. We applied this technique to 45-nm node high performance (HP) CMOS devices with a gate length of 32-nm. A reduction in the source-drain parasitic resistance achieves 8.8% / 5% of improvements in the saturation on-current (Ion) for PMOS / NMOS, and Ion = 750(P) / 1030(N) [muA/mum] for Ioff = 100 [nA/mum] at Vdd= 1.0V. We also demonstrated the advantages of this technique by evaluating the performance of ring oscillators, SRAM yields and accuracy of precision poly resistors from the LSI manufacturing point of view.

1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.