H. Morioka

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.

High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD

Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported. We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure. Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE. Electron and hole mobility enhancement can be balanced by aggressively scaled poly-Si pMOS gate height and SiN capped shallow trench isolation (STI) with SiN liner. A high performance 30 nm/33 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 937/1000 muA/mum and 490/545 muA/mum at Vd=1.0 V / Ioff=100 nA/mum, respectively

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

This paper presents a 65 nm CMOS technology for mobile multimedia applications. The reduction of interconnect capacitance is essential for high-speed data transmission and small power consumption for mobile core chips. We have chosen a hybrid ULK structure which consists of NCS (nano-clustering silica; k=2.25) at the wire level and SiOC (k=2.9) at the via level. Although NCS is a porous material, the NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bonding. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistors meet the electrical targets from the circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 /spl mu/m/sup 2/ small cell size has been achieved.

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Aggressively scaled 25 nm gate CMOSFETs for the 65 nm node are reported. We successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc.). Both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration. High drive currents of 840/1010 /spl mu/A//spl mu/m and CV/I values of 0.54/0.60 psec with 25/33 nm gate nMOSFETs were achieved at Vdd=1 V and Ioff=100 nA//spl mu/m. They are the best values among recent published papers.

Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs

We have investigated what effects randomly oriented and rotated poly-Si gate grains have on lateral carrier profiles in sub-50-nm MOSFETs by direct observations and electrical measurements. Since amorphous gates suppress random channeling penetration of pocket implants, we have increased effective mobility (40%), improved Vth roll-off characteristic (7 nm) and decreased Vth fluctuation (-26%)

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

This paper demonstrates high performance 35 nm gate length CMOSFETs for 65 nm technology node. The impact of vertical gate scaling on dopant activation in poly-Si gate and device performance is investigated. Total stress controls form both STI and interconnect improved the nMOS drive current up to 5-10% without degradation for pMOS. Excellent controlled 35 nm gate length CMOSFETs are achieved with a high drive current of 650 uA/um for nMOS and 310 uA/um for pMOS at Ioff=70 nA/um at supply voltage of 0.85 V. Low CV/I values of 0.85 ps for nMOS and 1.61 ps for pMOS are obtained. These results are competitive among the latest published data.

Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon

Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addition, we developed novel stack-SIN gate dielectrics by using bis-tertiarybutylamino-silane (BTBAS)/NH3. Novel stack-SIN gate dielectrics show higher immunity to negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime compared with conventional plasma nitrided silicon dioxide. These characteristic are originated from its unique nitrogen profile. The nitrogen concentration is over 22% at the surface of the dielectric and it rapidly decreases to 1% at the interface with a substrate. A high performance 30 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 1042 muA/mum and 602 muA/mum at Vd = 1 V / Ioff=100 nA/mum, respectively

Suppression of Defect Formation and Their Impact on Short Channel Effects and Drivability of pMOSFET with SiGe Source/Drain

The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step, the initial defect density is reduced, and by introducing a cap layer on a SiGe layer, the thermal stability of the SiGe layer is improved. The optimized devices enhance mobility 42% by maximizing the strain effect and provide better SCE characteristics by suppressing boron diffusion

Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

We have proposed inhibition mechanism of common Al-capping technique for pMOSFET threshold-voltage (Vth) control for the first time, and have established effective Ti-capping technique using metal gate and Hf-based high-k dielectrics. Ti-capping technique can adjust lower Vth than Al-capping one due to the suppression of counter dipole and solid solubility limit in doping. Moreover, Ti-capping technique can improve carrier mobility and negative bias temperature instability (NBTI). We have confirmed that Ti-doped devices achieve higher performance, and the technique is suitable for 32 nm-technology node and beyond.