H. Onodera

Characterization of WSix/GaAs Schottky contacts

The Schottky diode characteristics of WSix contacts on n‐type GaAs have been investigated and correlated to the film stress in WSix and crystallographic properties of the film. Experimental results show that (1) the high‐temperature stability of WSix/GaAs Schottky diode characteristics depends significantly on Si content; (2) WSix/GaAs contacts exhibit very high‐temperature‐stable Schottky diode characteristics at Si content around 0.60, and at this Si content no metallurgical interactions between WSix and GaAs are observed by 2‐MeV 4He+ Rutherford backscattering (RBS) measurements; (3) the optimum Si content for Schottky diode characteristics coincides with that for stress minimum in WSix; (4) the Schottky diode characteristics are not affected by whether WSix is crystallized or not, and a common feature of the regions where the Schottky diode characteristics are very high‐temperature stable is that each consists of single‐phase (W5Si3 secondary solid solution or amorphous).

TiW Silicide gate self-alignment technology for ultra-high-speed GaAs MESFET LSI/VLSI's

It has been found that TiW silicide film forms Schottky contacts on GaAs which are extremely stable even at temperatures of up to 850°C. Using this silicide for gate material, a novel self-alignment technique for GaAs MESFETs has been developed. A minimum propagation delay of 50 ps with 1.5-µ gate logic and successful fabrication of 1-kbit fixed address GaAs static memory cell arrays which are based on E/D type DCFLs indicate that TiW silicide gate self-alignment technology is a very promising candidate for achieving ultra-high-speed GaAs MESFET LSI/VLSIs.

40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

A 1.2V 40Gbit/s 4:1 MUX and 1:4 DEMUX are implemented in a in 90nm digital-compatible standard CMOS technology. The MUX and DEMUX operate from a 1.2V supply and draw 110mA and 52mA, respectively. Experimental results show a clear eye opening of 300mV/sub pp/ for the MUX and that of 540mV/sub pp/ for the DEMUX at 40Gbit/s.

A GaAs 1K static RAM using tungsten-silicide gate self alignment technology

This paper will report on a GaAs 1K static RAM using tungsten silicide gate self-aligned technology and ion implantation. Address access time of 4ns was obtained with power dissipation of 58mW.

Orientation effect of self‐aligned source/drain planar GaAs Schottky barrier field‐effect transistors

The effect of orientation on self‐aligned source/drain planar GaAs Schottky barrier field‐effect transistors (FET’s) has been investigated. The dependence of the threshold voltage of FET’s on gate length was measured for FET’s oriented in two perpendicular [110] directions. Both stress‐enhanced lateral spread of implanted ions and lateral diffusion at the gate material/GaAs interface are proposed as possible mechanism to account for the orientation effect. The experiments indicate that the preferred direction for the self‐aligned FET fabrication on a (100) substrate is [011].

A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS

This paper describes a 25 GHz clock buffer and 50 Gb/s 2-to-1 selector, which are implemented in 90 nm CMOS using 48 nm transistors, and operate off a 1 V supply. An inductor-peaked CMOS inverter is employed for the clock buffer. The selector is equipped with a tail transistor whose gate is switched by the rail-to-rail clock signal produced by the buffer.

A 43Gb/s 2:1 selector IC in 90nm CMOS technology

The 2:1 selector IC consists of three stages of input buffers, a 2:1 selector stage, and two stages of output buffers. By using multiple inductive peaking and selector architecture to suppress interference, the proposed circuit operates at a data rate of 43Gb/s and it is implemented in 90nm CMOS technology with 48nm transistors.

GaAs MESFET LSI design using E/D-DCFL circuits

GaAs MESFET LSI design using E/D-DCFL (enhancement/depletion-directly coupled FET logic) circuits is considered. Monte Carlo DC SPICE simulation is used to assess the effect of the FET parameter spread on the functional yield of a chip. It is found that the important factors for obtaining a high functional yield are strict control of the FET characteristics and the stability and uniformity of the supply voltage on the chip. The functional yield model, including the supply voltage drop, agrees well with the results obtained in experiments on a 5 K gate array IC fabricated with 0.8- mu m-gate BP-MESFETs.<<ETX>>

A high-transconductance self-aligned GaAs MESFET fabricated by through-AIN implantation

This paper describes a new technique for the fabrication of high-transconductance GaAs MESFETs. Tungsten-silicide gate, self-aligned GaAs MESFETs were fabricated on extremely thin channel layers formed by implantation through AlN layers on semi-insulating GaAs substrates. Transconductance of the through-implanted MESFETs showed 30- to 50-percent increase as compared with that of conventional self-aligned MESFETs and reached its maximum value at 300 mS/mm for 1-µm gate-length FETs. The uniformity of the threshold voltage across a 2-in wafer was also excellent with a standard deviation of 44 mV. Circuit simulation indicates that the advantage of these FETs becomes more crucial when used in a very large-scale integrated circuit (VLSI).

A 3-ns GaAs 4K &#215; 1-bit static RAM

A 3-ns 700-mW GaAs 4K × 1-bit static RAM has been developed using tungsten-silicide-gate self-aligned technology with a minimum design rule of 1.5 µm. A GaAs 1K × 1-bit static RAM, developed using the same technology, affords 1.0-ns minimum address access time and 300-mW power dissipation.