Kouichi Kanda

Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs

In sub 1 V CMOS designs, especially around 0.5 V CMOS designs, the on-state drain current of MOSFETs shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Together with the low threshold voltage less than 0.2 V in the low-voltage CMOS, a possibility of temperature instability increases. The paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFETs and 32-bit adder circuit in quarter micron CMOS technology with low threshold voltage of 0.25 V.

90% write power-saving SRAM using sense-amplifying memory cell

This paper describes a low-power write scheme which reduces SRAM power by 90% by using seven-transistor sense-amplifying memory cells. By reducing the bitline swing to V/sub DD//6 and amplifying the voltage swing by a sense-amplifier structure in a memory cell, the charging and discharging component of the power of the bit/data lines is reduced. A 64-kb test chip has been fabricated and correct read/write operation has been verified. It is also shown that the scheme can also have the capability of leakage power reduction with small modifications. Achievable leakage power reduction is estimated to be two orders of magnitude from SPICE simulation results.

Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)

The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-/spl mu/m FD-SOI process with low V/sub TH/ of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator.

40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

A 1.2V 40Gbit/s 4:1 MUX and 1:4 DEMUX are implemented in a in 90nm digital-compatible standard CMOS technology. The MUX and DEMUX operate from a 1.2V supply and draw 110mA and 52mA, respectively. Experimental results show a clear eye opening of 300mV/sub pp/ for the MUX and that of 540mV/sub pp/ for the DEMUX at 40Gbit/s.

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range

Quadrature injection-lockedLC dividers with either a Miller topology or an injection-lockedLC VCO topology are coupled with transconductors to enhance their locking range. The effect of the transconductance coupling is analyzed theoretically and through circuit simulation. Both topologies were fabricated by 90-nm CMOS technology with a target input center frequency of 20 GHz and output frequency of 10 GHz. The measured locking range for the Miller topology with transconductance coupling is 25.3%, compared to 20.9% without coupling. The measured locking range for the injection-locked LC VCO topology with transconductance coupling is 18.1%, compared to 12.9% without coupling. Moreover, power consumption for both dividers is 6.4 mW with a 1.2-V supply.

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

The recent rapid spread of smart-phone use has resulted in a strong demand for a multi-band RF part with reduced size and power consumption. In the creation of an ideal RF system-on-a-chip, the biggest challenge is to realize a fully integrated PA in CMOS. In conventional PAs in compound semiconductor technologies, face-up wire-bond assembly with off-chip matching components is typically used, but flip-chip packaging is more suitable for slim mobile phones in which low-profile components are desired as well as for future integration with an RF transceiver in which the same packaging scheme is widely used. The PA for GSM [1] was insufficient for our target, so we needed to greatly improve the linearity in order to comply with the W-CDMA standard, which has better frequency-usage efficiency. Conventional CMOS PAs only support a single band [2,3] or are for WLAN [4] where the output power level is low (typically about 20dBm). In this paper, we present a fully-integrated triple-band linear CMOS PA for W-CDMA. Its flip-chip package is just 3.5×4×0.7mm3, and the average current consumption is less than 20mA.

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications

The introduction of the IEEE802.15.6 standard (15.6) for wireless-body-area networks signals the advent of new medical applications, where various wireless nodes in, on or around a human body monitor vital signs. Radio communication often dominates the power consumption in the nodes, thus low-power transceivers are desired. Most state-of-the-art low-power transceivers support only proprietary modes with OOK or FSK modulations, and have poor sensitivity or low data rate [1,2]. In this work, a 15.6-compliant transceiver with enhanced performance is proposed. First, the data-rate is extended to 4.5Mb/s to cover multi-channel EEG applications. Second, while a best-in-class energy efficiency of 0.33nJ/b is achieved in the high-speed mode, a dedicated low-power mode reduces the RX power further in low-data-rate operation. Third, a sensitivity 5 to 10dB better than the 15.6 specification is targeted to accommodate extra path loss due to shadowing effects from human bodies.

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

Fabricated in 90nm CMOS, the chip consumes 545mW and has a pattern-balancing adaptive equalizer that is stable for any data patterns including those with a strong peak component at a single frequency. The adaptive equalizer yields a gain at fs/2 relative to fs/16 varying from -1.7 to 2.2dB for any 8B10B encoded Ethernet frames filled with a fixed data byte