R. H. Womack

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

A trench transistor cross-point DRAM cell

A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

Trench capacitor design issues in VLSI DRAM cells

Major issues involved in the optimization of trench capacitors for VLSI DRAMs are considered, using the previously described 4Mb DRAM cross-point Trench-Transistor Cell (TTC) as a vehicle. The effects of capacitor plate doping, trench etch angle and depth on the capacitance of the trench capacitor are studied. Pisces-II simulations show that there is adequate electrical isolation between adjacent cells, with a grounded substrate. Any tendencies for intercell leakage are further minimized, by reverse-biasing the substrate at-2.0V. High-resolution TEM and lattice imaging techniques are utilized to study the quality of oxide dielectric in the trench capacitor. In addition, a simple way of enlarging the capacitor area, in order to increase the storage capacitance, is presented.

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Trench capacitor leakage in Mbit DRAMs

The limitations on trench capacitors imposed by leakage mechanisms in high density DRAMs has been studied through simulations. The primary purpose of the work has been to investigate all possible leakage mechanisms and to determine the optimum substrate doping profile for which the trench capacitor leakage is sufficiently suppressed. The effect of all relevant structural, process and electrical parameters on the required substrate doping profile is also fully investigated. The substrate doping density at which impact ionization causes avalanche breakdown at the trench capacitor junction has also been estimated. It is shown that for trench spacing of 0.75 µm or more. an intermediate range of substrate doping concentrations can always be found for which both the trench leakage and the junction breakdown can be avoided.

Polysilicon transistors in VLSI MOS memories

The recent progress on the use of as-deposited, small grain LPCVD polysilicon transistors in VLSI memories is discussed with the emphasis on their applications for static and dynamic RAMs. Some process and device related issues are discussed. Successful implementation of an experimental stacked CMOS 64K sRAM proves the utility of these devices for three dimensional integration in a VLSI environment.

Trench transistor DRAM cell

A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 µm2using 1-µm design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAMs.

VB-5 comparison of accumulation and inversion mode LPCVD polysilicon MOSFET characteristics for memory applications

This paper compares the device characteristics of inversionand accumulation-mode small-grain LPCVD polysilicon transistors, as a function of various process parameters. Previous papers have reported on the fabrication of polysilicon transistors [ 11, [2] , and the dramatic improvement in the on-to-off current ratio upon grain boundary passivation [ 31 , [4 ] . We present data on the dependence of device characteristics such as subthreshold slope, leakage, and threshold voltage on process parameters such as channel and sourcedrain doping, polysilicon. film thickness, polysilicon grain growth conditions, and grain boundary passivation. An LPCVD polysilicon film, between 100 and 300 nm thick, deposited on 300 nm of thermal oxide, was implanted with B o r As, at doses between 6E12 cm-’ and 4E13 cm-’, to obtain various channel dopings. A 32-nm gate oxide was grown, and self-aligned source-drain As implants were performed using a 300-nrn P0Cl3 doped LPCVD polysilicon gate. Grain boundary passivation was achieved for some of the transistors [ 31. The subthreshold slopes for n-channel passivated devices, with W / L = 100/2 pm, in a 220-nm polysilicon film, are 220 320, and 3800 mV/decade for channel implants of 1E 13-cm-” B, zero, and lE13-cm-’ IP, respectively. The corresponding subthreshold slope for an unpassivated inversion-mode device (B-doped channel) is 750 mV/decade. Thus inversion-mode devices have a sharper turn-on than accumulation-mode devices, and passivation improves the subthreshold slope by more than a factor of two. The leakage is also lowest for the inversion-mode devices. The minimum leakage currents for VD = 5 V are 0.32 pA/pm, 7.0 nA/pm, and 13.0 pA/pm for channel implants of 1E13-cma2 I), zero, and l E 1 3 ~ m ~ P, respectively. However, inversion-mode devices also suffer f om lower drive currents. It is also observed that for an undoped channel, a higher source-drain doping gives a stronger dependence of leakage current on the gate voltage, presumably because of the higher field at the reverse biased drain junction. This leakage seems to be due to a field-enhanced detrapping of carriers and avalanche multiplication because of the high field at the drain end. Upon process parameter optimization, small-grain LPCVD polysilicon transistors yield good subthreshold slope and high on/off current ratio, allowing them to be used in a wide varie ty of potential applications such as high-density SRAM’s and DRAM’S, three-dimensional IC’s, and switching elements in panel displays. Since small-grain LPCVD polysilicon technology is cheaper, simpler, and more established than recrystallized silicon-on-insulator, there is a strong motivation to understand and improve these transistors.

Trench capacitor leakage in high-density DRAM's

The leakage current between trench capacitors for megabit dynamic MOS memories has been modeled and studied through simulations. The minimum substrate doping density, to limit the leakage current to 1 pA/µm, has been determined as a function of trench-trench spacing. The effect of all other relevant parameters on the required substrate doping density has also been investigated. Furthermore, the substrate doping density at which impact ionization causes avalanche breakdown at the trench capacitor junction has been estimated. It is found that, for trench spacing of 0.75 µm or more, one can always find an intermediate range of substrate doping concentrations for which both the trench-trench leakage and the junction breakdown can be avoided.