H. Y. Li

Achieving Stable Through-Silicon Via (TSV) Capacitance with Oxide Fixed Charge

Through-silicon via (TSV) is an important enabler for future 3-D integration of integrated circuits. TSV typically contains a high-aspect-ratio metal via embedded in silicon and electrically isolated from the silicon by a layer of dielectric liner hence forming a metal-oxide-semiconductor structure. The parasitic capacitance introduced by TSV must be kept as low as possible for low latency signal transmission. It is also equally important to ensure that the capacitance within the operating voltage is stable. It is shown that careful process tuning can induce the appropriate oxide fixed charge (|Qf| ~ 8.4 × 1011 cm-2) in order to shift the CV curve such that the TSV capacitance is kept stable at the value of accumulation capacitance (Cox) within the operating voltage range of interest (~0-5 V).

On the Impact of Through-Silicon-Via-Induced Stress on 65-nm CMOS Devices

Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm, respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between -55°C and 125 °C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

Ultrafine Pitch (6

In this letter, an evolution of high-density (>; 106 cm-2) bonded Cu-Cu interconnects of 6-μm pitch is successfully demonstrated using wafer-on-wafer thermocompression bonding. Cu sealing frame with excellent hermeticity is integrated to the bonded structures to promote bond reliability. Additionally, temporary passivation of Cu surface using self-assembled monolayer enhances the resistance against oxidation, which, in turn, enables moderately low-temperature bonding process at 300°C. Finally, thermal cycling test confirms the thermal stability of the 6-μm-pitch Cu-Cu daisy chain structure up to 1000 cycles. This work opens up new opportunity for wafer-level integration of bumpless Cu-Cu bonding to enable future high-bandwidth 3-D integrated circuit applications.

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One of challenge for the 3D integration by the TSV approach is the electroplating. Electroplating quality and time are important parameters for TSV cost and application. Solid Cu filling TSV (Through Si Via) with via diameter 20 μm and 65μm depth is achieved by the DC (directly current) electroplating within 40 minutes on 8 inch wafer.

) of Recessed and Bonded Cu–Cu Interconnects by Three-Dimensional Wafer Stacking

Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment data. With using the developed model, wafer warpage has been simulated and analyzed by considering different factors such as annealing temperature, Cu overburden thickness, TSV depth and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and increasing Cu overburden thickness. Such findings have been successfully used in the TSV process optimization to reduce wafer warpage after annealing process. Submodeling methodology has also been developed to determine wafer stress accurately. Wafer bending stress is larger at wafer surface and close to the TSV edge. Bending stress is higher at the edge of TSV with finer pitch.

Fast electroplating TSV process development for the via-last approach

The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling.

Wafer level warpage modeling methodology and characterization of TSV wafers

A thermal bonding based wafer-transfer-technology (WTT) has been developed and successfully applied to transfer active devices, RF-passive components and high density interconnect pre-fabricated by CMOS technology onto a flexible organic substrate. The intrinsic performances of transistors and interconnect are preserved with excellent reliability, and the RF-passive components are clearly demonstrated in much enhanced RF characteristics

3D interconnection process development and integration with low stress TSV

Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity (<1 mm separation) compared with several centim...

Successful transferring of active transistors, rf-passive components and high density interconnect from bulk si to organic substrates

The variation of through-silicon-via (TSV) capacitance caused by nonuniform hot-spot heating can lead to spatial circuit performance variation; this effect is undesirable for 3-D IC design. Hence, stable TSV capacitance is desired to overcome this issue. In this letter, stable TSV capacitance is achieved by utilizing Al₂O₃-induced negative fixed charge (|Q_f| = 7.44 × 10¹¹ cm^-2) at the Si-liner interface. This causes a positive shift in the flat-band voltage (ΔV_FB = 6.85 V) and results in the TSV operating in the stable accumulation capacitance region within operating voltage of interests (~0-5 V). The leakage current density of the TSV with Al₂O₃ layer and PETEOS liner is improved by ~10× after annealing in forming gas (N₂/H₂) at 300 °C for 30 min.

Heterogeneous 2.5D integration on through silicon interposer

RDL process becomes more and more important with through Si interposer (TSI) application in 3D packaging. RDL line/space needs to be shrinking with the increasing of device density. We had been developed low temperature (LT) damascene process for the RDL formation in 3D interposer integration. The sample failed at thermal reliability test. High temperature (HT) RDL was developed and demonstrated after TSV annealing temperature optimization in this paper.