Alastair David Trigg

Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.

Three Dimensional Stress Mapping of Silicon Surrounded by Copper Filled through Silicon Vias Using Polychromator-Based Multi-Wavelength Micro Raman Spectroscopy

Three dimensional (3D) stress distributions in Si, surrounded by copper (Cu) filled through silicon vias (TSVs) with various dimensions and pitches, are non-destructively characterized and stress contour maps generated at different depths using a long focal length, polychromator-based, multi-wavelength micro-Raman spectroscopy system. It was found that stress and crystallinity in Si (in both planar and depth directions) was strongly influenced by the proximity to a TSV, as well as, the dimensions of the TSV. In addition to characterizing semiconductor materials, Multi-wavelength micro-Raman spectroscopy was extremely effective for characterizing process-induced variations in crystalline stress and quality where 3D interconnects and packaging technology is introduced.

Study on Cu Protrusion of Through-Silicon Via

The through-silicon via (TSV) approach is essential for 3-D integrated circuit (3-DIC) packaging technology. TSV fabrication process, however, is still facing several challenges. One of the widely known challenges is via protrusion. Annealing a TSV wafer puts the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is forced out of the blind TSV. This phenomenon occurs because the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) surrounding it. Cu protrusion can lead to crack or delamination of the back-end-of-line, thus, it is a risky threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscopes and atomic force microscopes are used to observe the protrusion shape and measure the height. An electron backscatter diffraction technique is implemented to study the grain size distribution and evolution inside Cu vias. For the experiment, arrays of 5-

Design and fabrication of a reliability test chip for 3D-TSV

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Non-destructive testing of a high dense small dimension through silicon via (TSV) array structures by using 3D X-ray computed tomography method (CT scan)

TSVs are fabricated and annealed in nitrogen gas environment in different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then carried out. Based on the verified FEA methodology, several parametric studies are then conducted, including the effect of via diameter, depth, pitch, annealing temperature, and duration on Cu protrusion and TSV stress. The simulation results help to understand and solve the key problem in TSV fabrication process and reliability challenge.

In Situ Measurement and Stress Evaluation for Wire Bonding Using Embedded Piezoresistive Stress Sensors

A test chip has been designed and fabricated to validate the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). The test chip contains test structures designed to measure the electromigration performance of TSVs and microbump, thermal performance, stress in the chip as a result of thinning and die stacking, and corrosion related to moisture ingress. The structures are designed to facilitate failure analysis, allowing fault isolation to be done by electrical characterization as far as possible.

Work Function Tunability of Refractory Metal Nitrides by Lanthanum or Aluminum Doping for Advanced CMOS Devices

In the present study, high density TSV structures have been designed and fabricated with different diameter and depths, ranging from 2 to 60 µm and 50 to 100 µm respectively. The ratios of TSV diameter to space between TSVs are 1∶2, 1∶3 and 1∶4. Inspection of TSV structures at each processing step is very crucial to proceed to next step. 3D X-ray CT scan analysis has been employed to inspect TSV wafers at different processing steps. Detailed 3D X-ray CT scan analysis has been carried out on 20, 50 and 60 um TSV array structures. Using this method, it is possible to observe defect shape, size and distribution by conducting the virtual cross-section at desired location. Based on the detailed online failure analysis, TSV process development parameter are being fine-tuned and optimized.

Redistribution layer (RDL) process development and improvement for 3D interposer

A ball bonding process in wire bonding generally involves impact followed by ultrasonic (US) bonding prior to wedge bonding. During the ball bonding process, the impact force flattening the free-air ball introduces significant localized out-of-plane compressive stress on the pad and the low-k structure beneath. The subsequent process of US bonding induces in-plane and shear stresses to the structure. High induced stress during bonding is not desirable, as it may lead to pad damage or cratering of the silicon structure. In this paper, we report on studies conducted on using four piezoresistive sensors embedded underneath the center of the bond pad for the evaluation of in-plane and out-of-plane stresses, which covers both the impact and US stages during the ball bonding process. Different levels of impact force, bond force, bonding duration, and US power are investigated using gold wire bonding for feasibility and sensitivity studies of the stress sensors. Fast Fourier transform (FFT) and inverse FFT are used for noise filtering and to isolate the US signal yielding a continuous output signal from the in situ measurement of contact and US stages during the ball bonding process. It is found that the stress sensors are sensible to capture different impact force, bond force, bonding duration, and US power.

MEMS failure analysis and reliability

A lanthanum (La)-doped HfN is investigated as an n-type metal gate electrode on SiO2 with tunable work function. The variation of La concentration in (HfinfinLa1-x)Ny modulates the gate work function from 4.6 to 3.9 eV and remains stable after high-temperature annealing (900degC to 1000degC), which makes it suitable for n-channel MOSFET application. An ultrathin high-fc dielectric layer was formed at the metal/SiO2 interface due to the (HfinfinLa1-x)Ny and SiO2 interaction during annealing. This causes a slight reduction in the effective oxide thickness and improves the tunneling current of the gate dielectric by two to three orders. We also report the tunability of TaN with Al doping, which is suitable for a p-type metal gate work function. Based on our results, several dual-gate integration processes by incorporating lanthanum or aluminum into a refractory metal nitride for CMOS technology are proposed.

Effects of Annealing and Temperature on SGOI Fabrication Using Ge Condensation

RDL process becomes more and more important with through Si interposer (TSI) application in 3D packaging. RDL line/space needs to be shrinking with the increasing of device density. We had been developed low temperature (LT) damascene process for the RDL formation in 3D interposer integration. The sample failed at thermal reliability test. High temperature (HT) RDL was developed and demonstrated after TSV annealing temperature optimization in this paper.