Ha-Jin Lim

Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

For the first time, we have investigated the effect of ozone (O/sub 3/) pre-treatment on the bias temperature instability (BTI) characteristics of high-k gate dielectrics. We found that O/sub 3/ pre-treatment improved NBTI and the electrical characteristics of HfAlON gate dielectric. We suggest that O/sub 3/ pre-treatment effectively suppresses the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32 V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded. We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (/spl sim/1.1 V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

Dual High-k Gate Dielectric Technology Using Selective AlOx Etch (SAE) Process with Nitrogen and Fluorine Incorporation

We propose a novel Vth, control method for HfSiON (or HfO2) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlOx etch (SAE) process, we successfully integrate dual high-k gate oxide scheme; HfSiO/poly-Si stack for nMOS and HfSiO/AlOx/poly-Si stack for pMOS. Therefore, symmetrical Vth values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N 2 for nMOS and F for pMOS. Consequently, nMOS Vth of 0.35V and pMOS Vth of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by an extrapolated 10 years lifetime

Highly Manufacturable Single Metal Gate Process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 muA/mum for n/pMOS at Ioff =20pA/mum and Vdd=1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well

Behaviors and physical degradation of HfSiON MOSFET linked to strained CESL performance booster

The propensity of HCI and BTI degradation of HfSiON MOSFET on strained SiN-CESL performance booster is meticulously investigated. It is found that HCI and BTI lifetime of HfO based n/p MOSFET devices depend on hydrogen, initial Dit and plasma charging inherently related to the stress type of CESL fabricated with PECVD. In case for tensile CESL, n/p MOSFET devices far exceed reliability targets for both HCI and BTI. While compressive CESL on n/p MOSFET drastically depresses HCI and BTI lifetime.

Integration Friendly Dual Metal Gate Technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

We have successfully developed integration friendly dual metal gate process utilizing a dual thickness metal inserted poly-Si stacks (DT-MIPS) structure; poly-Si/TaN/HfON stacks for nMOS and poly-Si/capping metal layer(c-ML)/AlOx/TaN/HfON stacks for pMOS. First, in spite of different metal thickness on n/pMOS, a high-selectivity gate etch process can completely remove metal and HfON layers from the S/D active regions with negligible Si recess in both n/pMOS. Consequently, in both short and long channel devices, n/pMOS Vth values of ~plusmn0.35 V are obtained without counter channel doping. Moreover, excellent drive currents (620/250 muA/um for n/pMOS at Ioff=20 pA/um and Vdd=1.2 V) are obtained without using any mobility enhancement technique. Finally, we confirm that the estimated operation voltages for 10 years lifetime for both nMOS PBTI and pMOS NBTI are well beyond the 1.2 V.

Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis [MOSFETs]

For the first time, we evaluated the breakdown and conduction mechanisms of ALD HfSiON with TaN gate. In the unstressed HfSiON, hole current dominates the gate leakage current. Under the SILC condition, the electron trap generation from the band edge of the TaN gate and conduction band edge of the Si substrate is accelerated, resulting in an increase of electron current. After soft breakdown of the dielectric, the electron current is predominant in the gate leakage. We demonstrate that the electron tunneling current mainly contributes to the degradation and breakdown of HfSiON dielectric with TaN gate. The conduction mechanism of the electrons and holes is Fowler-Nordheim tunneling.