Sung-Kee Han

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

20nm DRAM: A new beginning of another revolution

For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.

HCI and BTI characteristics of ALD HfSiO(N) gate dielectrics as the compositions and the post treatment conditions

For the first time, we evaluate the HCI and BTI degradation of ALD HfSiO(N) gate dielectrics as the compositions and the post annealing conditions. The HCI and PBTI degradation are minimized at Hf to Si cycle ratio of 3 to 1 (Hf/(Hf+Si) = 0.75) and the post reoxidation annealing suppresses both degradations. It is believed that the HCI and PBTI degradation are related to the electron traps in the gate oxide. However, NBTI degradation is negligibly small compared to PBTI degradation. This indicates that the positive fixed charge generation or hole traps are not significant in ALD HfSiO(N) gate dielectrics.