Yun-Seok Kim

A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control

The novel technique to control the V/sub th/ of n/pMOS for HfSiO(N) in both poly-Si and MIPS (metal inserted poly-Si stack) gates is demonstrated. By adding AlO/sub x/ on HfSiO prior to poly-Si deposition, we successfully achieve symmetrical V/sub th/, values of 0.52V (nMOS), /-0.51V (pMOS) and high performance as I/sub on/, of 423uA/um for nMOS and 207uA/um for pMOS at I/sub off/=20pA/um. In addition, we find out that the ultra-thin and conformal TaN layer in MIPS gate does not contribute to the gate work function. By optimizing the TaN thickness, similar V/sub th/ values, compared to poly-Si gate, are achieved. Consequently, the measured saturation currents at I/sub off/=20pA/um are 430uA/um for nMOS and 250uA/um for pMOS. Both issues of PBTI for HfSiO/AlO/sub x//poly-Si structure and NBTI for HfSiO/AlO/sub x//MIPS structure are resolved by optimizing the post deposition annealing condition and using ozone interfacial oxide, respectively.

Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

For the first time, we have investigated the effect of ozone (O/sub 3/) pre-treatment on the bias temperature instability (BTI) characteristics of high-k gate dielectrics. We found that O/sub 3/ pre-treatment improved NBTI and the electrical characteristics of HfAlON gate dielectric. We suggest that O/sub 3/ pre-treatment effectively suppresses the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32 V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded. We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (/spl sim/1.1 V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

Improved current performance of CMOSFETs with nitrogen incorporated HfO 2 -Al 2 O 3 laminate gate dielectric

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.

Dual High-k Gate Dielectric Technology Using Selective AlOx Etch (SAE) Process with Nitrogen and Fluorine Incorporation

We propose a novel Vth, control method for HfSiON (or HfO2) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlOx etch (SAE) process, we successfully integrate dual high-k gate oxide scheme; HfSiO/poly-Si stack for nMOS and HfSiO/AlOx/poly-Si stack for pMOS. Therefore, symmetrical Vth values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N 2 for nMOS and F for pMOS. Consequently, nMOS Vth of 0.35V and pMOS Vth of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by an extrapolated 10 years lifetime

Practical next generation solution for stand-alone and embedded DRAM capacitor

For the first time, MIS capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are successfully demonstrated. The effective oxide thickness (EOT) of 21 /spl Aring/ with an acceptably low leakage current has been achieved for a cylinder-type MIS capacitor. The EOT of 21 /spl Aring/ is the smallest value reported for MIS capacitors with TiN electrodes regardless of dielectric material. We have confirmed the feasibility of reducing EOT in spite of the simple process without a pre-deposition treatment. HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is also useful for SIS capacitors and can satisfy the needs of MIM capacitors for the next generation without changing electrode material.

Characteristics of ALD HfSiO/sub x/ using new Si precursors for gate dielectric applications

We have successfully developed a process for ALD HfSiO/sub x/ that can provide excellent compositional control by using new Si precursors, Si/sub 2/Cl/sub 6/ (HCDS) and SiH[(CH/sub 3/)/sub 2/]/sub 3/ (tDMAS). In addition, comparisons of electrical properties of HfSiO/sub x/ using two Si precursors have been performed. CMOSFET with HfSiO/sub x/ using HCDS results in better reliability characteristics than tDMAS. Superior electron and hole mobility (100% and 90% of universal curve at 0.8MV/cm) are also achieved with HCDS. Consequently, HCDS has the potential to be used as a Si precursor for ALD HfSiO/sub x/.

HCI and BTI characteristics of ALD HfSiO(N) gate dielectrics as the compositions and the post treatment conditions

For the first time, we evaluate the HCI and BTI degradation of ALD HfSiO(N) gate dielectrics as the compositions and the post annealing conditions. The HCI and PBTI degradation are minimized at Hf to Si cycle ratio of 3 to 1 (Hf/(Hf+Si) = 0.75) and the post reoxidation annealing suppresses both degradations. It is believed that the HCI and PBTI degradation are related to the electron traps in the gate oxide. However, NBTI degradation is negligibly small compared to PBTI degradation. This indicates that the positive fixed charge generation or hole traps are not significant in ALD HfSiO(N) gate dielectrics.

Mass production worthy HfO/sub 2/-Al/sub 2/O/sub 3/ laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs

For the first time, we successfully demonstrated MIS capacitor with ALD (Atomic Layer Deposition) grown HfO/sub 2/-Al/sub 2/O/sub 3/ laminate film using Hf liquid precursor (Hf(NEtMe)/sub 4/) with EOT of 22.5 /spl Aring/ and acceptable leakage currents (1.0 fA/cell at 1.65 V) which is comparable to the smallest reported value. Advantages of Hf(NEtMe)/sub 4/ liquid precursor for DRAM capacitor dielectric are excellent step coverage (94% on high aspect ratio(>40:1)) and reasonable throughput (over two times higher than that of HfCl/sub 4/ solid precursor). This study will provide practical solution for chip-making industry in terms of mass production worthy process for sub-100 nm DRAM capacitor.

PBTI & HCI characteristics for high-k gate dielectrics with poly-Si & MIPS (metal inserted poly-Si stack) gates

Reliability characteristics of high-k gate dielectrics with poly-Si gates and metal inserted poly-Si stack (MIPS) gates are investigated in terms of positive bias temperature instability (PBTI) and hot carrier injection (HCI) characteristics. The results indicate that the dopants (P or As) from the poly-Si severely degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS structure, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. For the same reason, the worst HCI condition of high-k/poly-Si structure is V/sub g/=V/sub d/ instead of V/sub g/ at I/sub sub/spl I.bar/max/, while that of high-k/MIPS structure is V/sub g/ at I/sub sub/spl I.bar/max/.

Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis [MOSFETs]

For the first time, we evaluated the breakdown and conduction mechanisms of ALD HfSiON with TaN gate. In the unstressed HfSiON, hole current dominates the gate leakage current. Under the SILC condition, the electron trap generation from the band edge of the TaN gate and conduction band edge of the Si substrate is accelerated, resulting in an increase of electron current. After soft breakdown of the dielectric, the electron current is predominant in the gate leakage. We demonstrate that the electron tunneling current mainly contributes to the degradation and breakdown of HfSiON dielectric with TaN gate. The conduction mechanism of the electrons and holes is Fowler-Nordheim tunneling.