Hyewon Shim

Technology scaling on High-K & Metal-Gate FinFET BTI reliability

High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling. Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.

Hot carrier reliability characterization in consideration of self-heating in FinFET technology

A severity of hot carrier injection (HCI) in PFET becomes worse than NFET at elevated temperatures. This new observation is further found to be due to the coupled self-heating effects (SHE) during DC HCI stress (also a higher Ea in PFET HCI), rather than the negative bias temperature instability (NBTI) effect during HCI stress. Furthermore, in order to guarantee the precise estimation of HCI under circuit level AC condition, a new empirical HCI lifetime model decoupled from the SHE is proposed, which is further verified by the Si data from nanosecond pulsed waveform HCI stress and Ring Oscillator stress results.

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.

Reliability characterization of 10nm FinFET technology with multi-V T gate stack for low power and high performance

We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-VTs through work function engineering is presented. Comparable intrinsic BTI, HCI and TDDB can be achievable vs. 14nm node, while transistors with different VT-types exhibit no extrinsic issues, can support different Vmax. Scaled taller and narrower fin shape increases the transistor self-heating which enhances PMOS HCI and on-state TDDB, yet can be mitigated in realistic circuit operations including AC mode which was further validated with modeling [1]. SRAM and product reliability results including SER also exceeds goal.

Case Study: Verification Framework of Samsung Reconfigurable Processor

The SRP (Samsung Reconfigurable Processor) is a high-performance, low-power digital signal processor that supports two different operating modes: the VLIW (very long instruction word) mode for running control-intensive code and the CGA (coarse-grained reconfigurable array) mode for running computation-intensive code. In the SRP, an application starts in the VLIW mode, and then may switch back and forth many times between the CGA mode and the VLIW mode throughout its lifetime. In order to support this switching back and forth seamlessly, our C compiler for SRP is capable of generating an executable binary that contain codes for both VLIW and CGA modes. The unusual complexity of SRP verification originates from the unconventional processor architecture/micro-architecture and the complexity of our compiler. In order to manage the unconventional burden that confronts SRP verification engineers, we have aimed to build a scalable verification framework that is both flexible and efficient. In this paper, we report our experience so far, including our effort to be systematic and thorough in our approach.

Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-V T gate stack

Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for VT modulation in 10nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14nm technology were observed in both DC and AC operations. As BTI-induced VT variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing Vmin shift. Robust 10nm SRAM and product level HTOL reliability up to 500h were demonstrated.

Scenario-based set-level HTOL test (ASH III) for product quality and reliability qualifications on high-speed APs

In a succession of the set level stress test for high speed mobile application processor (AP) reliability [1], At-Speed HTOL (ASH) incorporated by user conditions was employed to realistically project the field failure rate of product. Using the worst case-scenario test with different frequency and operation duty, the failure modes veiled behind the conventional HTOL can be surfaced and then reconciled, which is further evolved as a failure screening technique during volume production. In addition, the simulation methodology to determine product Vmin-guardband (GB) in pre-silicon phase is also developed and compared to the Product Vmin-GB results. The results of ASH with scenario test can extend our understanding of an effective methodology to ensure robust design from design for test (DFT) and to achieve decent field failure target.

Mismatch circuit aging modeling and simulations for robust product design and pre-/post-silicon verification

As technology scales down, PMOS NBTI-induced mismatch, in addition to the NBTI mean-shifts and time0-Vt variation, is critical for designing circuitry having matched pair transistors, such as OP amplifier. This paper covers mismatch aging models incorporated into design simulation tool for PMIC products and used the Monte-Carlo simulation to consider process and systematic variations for robust design. Circuit simulation for PMIC OP Amp and its output characteristics were investigated and then further validated through the post-silicon HTOL stress. The pre-silicon simulation further enables to optimize HTOL stress conditions.