Haining S. Yang

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Strained silicon NMOS devices with embedded source/drain

Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions

STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET

Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Structure and method to enhance stress in a channel of cmos devices using a thin gate

Method of making strained channel CMOS transistors having lattice-mismatched epitaxial

BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT

Structure and method to form semiconductor-on-pores (sop) for high device performance and low manufacturing cost