Xinlin Wang

Electrostatic analysis of carbon nanotube arrays

In order to improve the performance of carbon nanotube field effect transistors (CNFETs), a nanotube array should be used. For a densely packed array of nanotubes, screening by nearby tubes affects the capacitance per tube. The gate-to-channel capacitance for a nanotube array of three different gate electrode configurations was examined in this study. Simulation results show that a wrap-around gate gives the largest gate-to-channel capacitance among the three gate configurations. A bottom gate structure, in which carbon nanotubes are unpassivated, presents a distinct electrostatic disadvantage of the weakest gate control. For a top gate structure, we found that an optimum design point exists for the pitch, which is defined as the distance between the centers of adjacent nanotubes, to get the largest gate capacitance per unit area.

Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design

In this letter, the random dopant fluctuation effect in ultrathin-body (UTB) fully depleted/silicon-on-insulator (FD/SOI) devices is analyzed. We show that due to larger variability and asymmetry in threshold voltage V/sub t/ distribution, it will be difficult to use UTB FD/SOI devices for sub-50-nm static random access memory (SRAM) design. Using thinner buried oxide (BOX) FD/SOI devices, the asymmetry in the V/sub t/ spread can be reduced. We present a viable concept of FD/SOI SRAM and predict that a thin-BOX device is the optimal FD/SOI structure for SRAM in sub-50-nm technology nodes.

Gate capacitance optimization for arrays of carbon nanotube field-effect transistors

In this paper, three different gate electrode configurations of CNFETs are studied by calculating the capacitance per tube of carbon nanotube arrays. We then show, that an optimal design point can be found a practical configuration.

Device scaling of high performance MOSFET with metal gate high-k at 32nm technology node and beyond

In this work, two different methodologies are used to quantitatively evaluate devices with metal high-k gate dielectrics for their scaling benefits over conventional polysilicon gate devices. For each method, device characteristics and ring oscillator delay calculations are performed. Our results show that aggressive channel length scaling continually provides transistor performance gain with the use of metal gate high-k technology. A band edge work function for the metal gate offers potential benefits for device scaling over conventional polysilicon gates for high performance (HP) application at the 32 nm CMOS technology node and beyond.

Gate-dielectric permitivity and metal-gate work-function tradeoff in L/sub met/=25nm PDSOI device characteristics

Short-channel (L=25nm) silicon-on-insulator (SOI) device performances over a range of gate work function from band edge to midgap and a range of gate-dielectric permittivity from 3.9 to 15 are studied using a two-dimensional simulator that takes into account quantum-mechanical effects. A tradeoff between metal-gate work-function requirements, gate-dielectric permittivity, and device design criteria is presented. For a high-performance device design criteria, device performance benefits are also quantified as a function of gate work function and gate-dielectric permittivity. The results suggest that the maximum benefits can be obtained even when the metal-gate work function is within 110 meV (90 meV) below (above) the conduction (valence) band edge for 25-nm SOI nMOSFETs (pMOSFETs).

A Practical Approach to Modeling Strained Silicon NMOS Devices

Parameters for a generalized mobility model are extracted from hardware measurements of strained silicon NMOS devices. Only the phone limited mobility parameter was shown to vary with amount of strain in the silicon.Using results of the mobility model fitting, simulations of strained and unstrained silicon devices were performed. These simulations indicated that strained silicon devices should have improved short channel control as well as yield a minimum of 50% improvement in on current.

Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond

In this work, we investigate multiple FIN FinFET source/drain designs to reduce series resistance and source/drain-to-gate capacitance. The tradeoffs between the increased parasitic capacitance and reduced parasitic resistance are explored using 3D device simulations.

Strained SiGe/Ge Buried Channel pMOSFETs Design For High Performance Applications

Introduction Dramatic hole mobility enhancement has been reported in strained-SiGe (s-SiGe) pFETs [1-5]. SiGe MOSFETs normally require a Si cap layer between the SiO2 and the SiGe layer to improve the oxide/semiconductor interface quality [6]. Since the drive current improvement of s-SiGe buried channel (BC) devices depends upon both the total inversion charge and the mobility enhancement in the buried channel, it is critical to optimize the charge distribution in the SiGe channel region, where the hole mobility is enhanced. On the other hand, the increased distance between the gate and channel makes the BC device with Si cap difficult to scale to short channel length. In this work, the channel design space and scalability of s-SiGe-BC p-MOSFETs is examined by simulations. Channel doping profiles and Si cap layer thickness are optimized to maximize drive current improvement and short channel effect (SCE) control at sub30nm gate length for high performance CMOS applications.

Hole Mobility Enhancement Modeling and Scaling Study for High Performance Strained Ge Buried Channel PMOSFETs

In this work, we simulated the long channel Ge-buried channel PMOSFETs by using driftdiffusion equation and calibrated the commonly used silicon mobility model to take buried channel hole mobility enhancement into account. 2D simulations were performed to study the channel design space for strained Ge buried channel PMOSFETs and two different buried channel structures were proposed to control short channel effect (SCE) down to 30nm channel length.