Dureseti Chidambarrao

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure

A novel device structure containing a SiGe stressor is used to impose tensile strain in nMOSFET channel. 400MPa of uniaxial tensile stress is induced in the Si channel through elastic relaxation/strain of the SiGe/Si bi-layer structure. This strain results in 40% mobility enhancement and 15% drive current improvement for sub-60nm devices compared to the control device with no strain

Stresses in silicon substrates near isolation trenches

We describe a methodology for obtaining stresses near isolation trenches in silicon considering the entire trench forming process. A two‐dimensional plane strain finite element stress analysis is performed for a trench with a thermal SiO2 sidewall and polysilicon ‘‘fill’’ which includes the cumulative stresses from the superposition of (i) residual stresses from the thermal oxidation step, (ii) the intrinsic stress from the polysilicon deposition, and (iii) stresses due to the coefficient of thermal expansion mismatch between SiO2 and silicon during the temperature cycles involved in the process. The thermal oxidation step is simulated using a two‐dimensional nonlinear viscoelastic program novel [in Proceedings of the Second International Symposium on Process Physics and Modeling in Semiconductor Technology, edited by G. R. Srinivasan, J. D. Plummer, and S. T. Pantelides (Electrochemical Society, Pennington, NJ, 1991), p. 772], that produces the oxide shape and stress at the oxide‐silicon interface which ...

Dual stress liner enhancement in hybrid orientation technology

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.

Effects of Peierls barrier and epithreading dislocation orientation on the critical thickness in heteroepitaxial structures

We have extended the mechanical equilibrium theory of J. W. Matthews and A. E. Blakeslee [J. Cryst. Growth 27, 118 (1974)] (MB) for determining the critical thickness in semiconducting heteroepitaxial films by including the effect of the Peierls barrier. The new formulation allows an evaluation of the dependence of critical thickness on the orientation of epithreading dislocation, and a comparison of theoretical predictions with measurements indicates that a knowledge of the epithreading dislocation orientation is necessary in predicting critical thicknesses in heteroepitaxial structures. In this formulation, the effect of the Peierls barrier is to bring the theoretical critical thicknesses closer to experimental values as compared to the predictions of the MB theory.

Design of high performance PFETs with strained si channel and laser anneal

The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D. And for the first time, we have demonstrated that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. Our study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyond

The effect of current density, stripe length, stripe width, and temperature on resistance saturation during electromigration testing

Resistance saturation as a function of current density, stripe length, stripe width, and temperature is investigated for a two-level structure with Ti/AlCu/Ti/TiN stripes and interlevel W stud vias. A simple model based on first principles is presented, which relates the maximum fractional resistance change to the current density and stripe length. Experimental results for stripe lengths of 30, 50, 70, and 100 μm are in good agreement with the model predictions. Estimated void sizes based on the resistance saturation data are consistent with the actual void sizes determined from scanning electron microscopy analysis. A weak temperature dependence is found for 0.33 μm-wide samples in the range 170–250°C, while a strong width dependence is observed between 0.33 and 1.50 μm- wide samples. The width dependence is qualitatively explained in terms of a relaxed bulk modulus that depends on the aspect ratio of the interconnect lines.

(110) channel, SiON gate-dielectric PMOS with record high I on =1 mA/μm through channel stress and source drain external resistance (R ext ) engineering

This paper presents for the first time (110) PMOS characteristics without R_ext degradation, allowing investigation of fundamental mobility and demonstration of drive current I_on in excess of 1mA/mum at I_off =100 nA/μm.

Analysis of systematic variation and impact on circuit performance

Yield loss due to process variations can be classified as catastrophic or parametric. Parametric variations can further be random or systematic in nature. Systematic parametric variations are being projected as a major yield limiter in sub- 65nm technologies. Though several models exist to describe process-induced parametric effects in layouts, there is no existing design methodology to study the variational (across process window) impact of all these effects simultaneously. In this paper, we present a methodology for analyzing multiple process-induced systematic and statistical layout dependent effects on circuit performance. We describe physical design models used to describe four major sources of parametric variability - lithography, stress, etch and contact resistance - and their impact on device properties. We then develop a methodology to determine variability in circuit performance based on integrating the above device models with a circuit simulator like SPICE. A circuit simulation engine for 45nm SOI devices is implemented, which shows the extent of the impact of layout-dependent systematic variations on circuit parameters like delay and power. Based on the analysis, we demonstrate that all systematic effects need to be simultaneously included to match the hardware data. We believe a flow that is capable of understanding process-induced parametric variability will have major advantages in terms of improving physical design and yield in addition to reducing design to hardware miscorrelations and advantages in terms of diagnosis and silicon debug.

On the retention time distribution of dual-channel vertical DRAM technologies

In this paper, we discuss unique opportunities in vertical transistor DRAM technology for retention time optimization. By fully utilizing the asymmetric vertical device design, we demonstrate that shallow Arsenic bitline junction, reduced buried strap outdiffusion, and locally lowered p-well concentration can be incorporated in vertical DRAM transistors to pave the scaling path without degrading retention time. A methodology to probe storage node side leakage current by the use of gated-diode measurements is established. Various mechanisms that impact retention time distribution are discussed. Furthermore, we demonstrate that the degradation of tail retention time due to high junction electric field can be minimized by aggressively lowering the junction depletion volume and defect levels.