Haiyun Xue

Parasitic parameter extraction and modeling of via of high speed differential pair

Since high speed digital signal interconnection usually consists of differential transmission lines and pairs of via, signals passing through pairs of via need carefully handling for via can be either capacitive or inductive. The modeling of high speed via is critical to match the impedance of a pair of via and differential transmission line. Parasitic parameters of a pair of via such as capacitances and inductances can be extracted by Q3d, a high performance EM parameter extraction software. Several variables are analyzed: the diameter of via, pad, anti-pad, space between the pair of via and position of ground via around the differential signal via. From the simulation results, parasitic parameters have a significant change with these variables changed. At the same time, TDR (Time domain reflection) and S parameter are also simulated by HFSS to verify the parasitic parameters effects. Parameter extraction and modeling with a pair of via is a helpful way for via optimization, which is commonly used in high speed digital signal interconnection, high frequency transceiver and many application areas.

Hybrid modeling method for power integrity simulation and analysis of multilayer electronic packages

In this paper, an efficient hybrid modeling method is presented for power integrity analysis of multilayer printed circuit boards (PCBs) and advanced electronic packages, with multiple power-ground planes, multiple vias, and external loads such as decoupling capacitors. Each parallel-plate pair, which consists of two consecutive conductor plates functioning as either power or ground in the PCBs or packages, is modeled as 2D generalized transmission line equations (GTLE). Equivalent circuits are used to model the vias and external loads. Numerical validation reveals that the hybrid modeling method produces accurate simulation results with much less central processing unit time and memory requirements than 3-D full-wave approaches.

Design and Implementation of a High-Coupling and Multichannel Optical Transceiver With a Novel Packaging Structure

Short-reach optical interconnection mainly focuses on the power consumption, the cost, and the volume. According to these requirements, the design and implementation of a multichannel transceiver are presented in this paper. In this paper, a high-coupling method without the 90° beam deflection is proposed so as to reduce the total power consumption to 0.9 W. Moreover, only the mature and low-cost packaging methods such as wire bonding and flip chip are adopted to satisfy the requirement of the optical coupling, which reduces the cost. Finally, the designed transceiver retains a small size of

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

28\times 16 \,\, \times

A Surface Mounting Embedded Optical Transceiver with Bi-Directional Data Rate of Eight Channels × 10 Gbps

3 mm3. To ensure normal function of the transceiver, the organic substrate is carefully designed, and the post-design simulation is conducted to characterize the electrical performance. At last, the test results show that the optical transceiver with this novel packaging structure is able to transmit the data at 10 Gb/s per channel successfully.

Reliability research on optoelectronics packaging

ABSTRACT With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth–distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

Electrical Research of Silicon Substrate Packaging Technology Based on the Cavity

Abstract The bi-directional data rate is investigated of an eight-channel × 10-Gbps optical transceiver with a size of 15 mm × 15 mm × 6 mm and ball grid array package form that was designed and fabricated. A passive optical coupling method is designed based on a coupling lens array, which is transformed to substrate through a carrier. This electrical performance is characterized through a 3D full wave simulation and shows great advantages compared with traditional pluggable optical transceivers. Experimental eye diagram measurement in loop-back mode via a 2-m-long multi-mode fiber array shows an eye width of 51.984 ps at a bit-error rate order of 10−12, which proves the transceivers ability for 10.3125-Gbps data transmission.

Design and Fabrication of Feasible 3D Optoelectronics Integration Based on Embedded IC Fanout Technology

Optoelectronic packaging is a challenge for optoelectronic device and optoelectronic integration. In the packaging level, optical under fill compound, optical fiber array, micro lens, silicon carrier and substrate effects on the thermal, optical and reliability performance of optoelectronic packaging. To prepare this challenge, a wide range of analysis and expertise for integrated optoelectronics, thermal and power management should be done. In this paper, reliability quality is researched based on parallel optical transceiver SiP. Then glue including under fill compound, optical fiber fixed and wire bonding glue is tested under 85 ° C/85 RH and -40 to 85° C thermal shock conformed with TELCORDIA standard. Also dielectric constant is measured for high frequency application. A 8 channel transceiver is fabricated with 80Gbps two way bandwidth. The eye diagram of 10Gbps of transceiver is tested from 25 to 60° C. Some results are discussed and some suggestion given is helpful on design of the reliability of optoelectronic packaging.