Yunyan Zhou

The electrical design of high-speed and high-density ASIC package

This paper introduces a package of a high-speed and high-density switching ASIC with over 1000 pins and hundreds of high-speed transmission lines crowded in two layers of the substrate, and also demonstrates Signal Integrity (SI) and Power Integrity (PI) implementation. In order to route the transmission lines with minimum distortion, crosstalk and attenuation, routing is co-designed with die and BGA maps. To guarantee that over a hundred transmission lines will be matched identically, each transmission line is designed to have a corresponding continuous return path routed among integrated copper shapes. Various routing schemes designed to take advantage of the physical and electrical performance of materials and structures are also implemented to optimize the performance of the transmission line. Various simulations are carried out on test segments to evaluate performance and signal integrity in the frequency and time domains.

An electrical design and fabrication of a 12-channel optical transceiver with SiP packaging technology

This paper presents an electrical design of a 6.25Gbps×12-channel parallel optical transceiver with SiP packaging technology. Considering such high speed, a low impedance and low noise power distribution network (PDN) is designed to suppress simultaneous switching noise (SSN) and a novel embedded capacitor filter is used to replace the conventional power supply filter. To minimize the impedance discontinuity of electrical channels, a signal integrity (SI) design flow based on Electromagnetic Analysis Method and Circuit Analysis Method is proposed. Following this design flow, the high speed link performs on a large bandwidth. With the electrical design, the optical transceiver is fabricated and tested.

Power integrity simulation for SiP using GTLE

Power integrity (PI) simulation for system-in-package (SiP) is a bottleneck in SiP design flow. This paper presents a novel numerical algorithm for PI simulation in packaging structures. This algorithm is based on 2D Generalized Transmission Line Equation (GTLE), Finite Difference Frequency Domain (FDFD) and mesh division technique. The power distribution network is simulated using mesh division technique where the model of power distribution network is obtained by regarding each cell as a 2D transmission line. 2D GTLE is a group partial equation about voltage and current density distribution on a power/ground plane pair. After reduction, the voltage equation for 2D GTLE is obtained, which is a Helmholtz equation. One method to solve the Helmholtz equation is by the finite-difference scheme. The 2D Laplace operator can be approximated to solve the voltage equation. In this paper, the fringe effect is modeled by the addition of cells around edges which is efficient and easy to implement. Finally, the methodology described in prior sections has been implemented in a CAD tool. The results from our method were compared to those from a full-wave simulator to show efficiency in power integrity simulation.

Hybrid modeling method for power integrity simulation and analysis of multilayer electronic packages

In this paper, an efficient hybrid modeling method is presented for power integrity analysis of multilayer printed circuit boards (PCBs) and advanced electronic packages, with multiple power-ground planes, multiple vias, and external loads such as decoupling capacitors. Each parallel-plate pair, which consists of two consecutive conductor plates functioning as either power or ground in the PCBs or packages, is modeled as 2D generalized transmission line equations (GTLE). Equivalent circuits are used to model the vias and external loads. Numerical validation reveals that the hybrid modeling method produces accurate simulation results with much less central processing unit time and memory requirements than 3-D full-wave approaches.

Power integrity simulation for multilayer power distribution networks based on GTLE and via model

In high-speed applications, electronic packages usually contain multilayer power-ground planes with large number of P-G vias to provide a low-impedance path for the power distribution system between the PCB and the die. The transient current injected into the P-G planes can induce unintentional voltage fluctuations in the power distribution network of the packages. The undesired voltage fluctuations can be significant even for the packages with solid P-G planes due to the return currents of switching input/output lines. A major problem arising in power distribution networks is simultaneous switching noise (SSN) which is induced by the power and ground inductance. This paper presents a numerical approach that combines the 2D generalized transmission line equations (GTLE) method and multi-layer finite-difference frequency-domain (FDFD) method to model and analyze the two-dimensional electromagnetic problem arising in multilayered power distribution planes. The results of our analysis method are compared to those from a full-wave simulator to show efficiency in power integrity simulation.

Signal integrity design and validation for multi-GHz differential channels in SiP packaging system with eye diagram parameters

Differential interconnect lines in multi-gigabits system in package (SiP) packaging system are studied in this paper. The performance of interconnect lines can be easily estimated with jitter and eye opening using the eye diagram that is very helpful metric. To maintain good eye-diagram with high voltage swing and low timing jitter, a signal integrity (SI) design flow of SiP is proposed based on eye-diagram parameters. To validate the influences of SI design to eye-diagrams, the relationship between the parameters of eye diagram and the structures of the impedance discontinuities physical elements such as vias, SMT pads are studied by a combination of software simulation and hardware validation. Some SI design rules are stipulated. As an example, a 4-channel × 10Gbp/s/channel optical transceiver in an SiP package is designed.

Optimization Design of 2.5D TSV Package Using Thermo-Electrical Co-Simulation Method

In this paper, a 2.5D TSV (through silicon via) package is de-signed for handheld device. A high performance Application Processor die and a Memory die with the sizes of 7.535×7.616×0.15 mm3 and 7.336×3.604×0.15 mm3, respectively, are integrated on a silicon interposer with a large number of TSVs. The backside and front of the interposer have one and two layers of redistribution layer (RDL), respectively. Each layer of RDL is about 3~5 μm and the minimum line width / pitch of the RDL in the interposer are 10 μm / 10 μm. In order to investigate the thermal performance of the package, IR drop of Power and Ground (P/G) Nets of the Processor and Memory dies, and the mutual effects of them, the paper conducts the following researches: First of all, only thermal simulation is done to investigate the thermal performance of the 2.5D TSV package using Cadence Sigrity PowerDC. The highest junction temperatures of Processor and Memory dies are evaluated. When the ambient temperature is 25°C, the junction temperatures of Processor and Memory dies are 62.7°C and 56°C, respectively, which are relatively higher for handheld device. Then, thermal and optimization designs are conducted to improve the thermal performance of the 2.5D TSV package. An aluminum heat spreader is employed, attached to the top surface of the 2.5D TSV package through high heat conductive thermal interface material (TIM). The effects of heat spreader size on the highest junction temperatures of Processor and Memory dies are studied and a heat spreader size of 60×60×2 mm3 is chosen. Thirdly, thermal simulation and thermo-electrical co-simulation are compared to study the effects of P/G Nets of the both dies on the thermal performance of the 2.5D TSV package. It is found that P/G Nets could increase the junction temperature of the both dies. Fourthly, IR drop analysis and thermo-electrical co-simulation are compared to study the effects of the heat dissipation issues of the package on the IR drop of P/G Nets of the both dies. The study shows that the heat could increase the IR drop of P/G Nets of the both dies and IR drop of VDDCPU of the Processor die is the biggest. Fifthly, aiming at the VDDCPU of Processor die, optimization design is carried out to reduce the IR drop of VDDCPU. After optimization, IR drop of VDDCPU decreases by 45.3%. IR drop decreases to an acceptable value. Therefore, P/G Nets of the dies should be considered when conducting thermal simulation of the package, and heat dissipation issues of the package should also be considered when analyzing IR drop of P/G Nets of the dies.

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

ABSTRACT With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth–distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

A GTLE and FDFD algorithm for analysis of power integrity in PCBs and packages

The numerical simulations of power integrity in electronic packages become more and more significant, which help us to understand the characteristic of power distribution network. In this work, a simple and efficient method synthesizing 2D generalized transmission line equations (GTLE) and finite-difference frequency-domain (FDFD) is proposed for power integrity simulation. The combined method can simulate power/ground plane pair surface mounted with lumped circuit elements such as decoupling capacitor. Several numerical results are presented compared to HFSS. Validation of the proposed method is demonstrated by the results.

A new measurement method and electrical design for high density optoelectronics integration

This paper describes a parallel test method based on a cross-point switch which can be programmed to control signal path and the number of switches to be opened according to the number of channels to be tested. In this method, at the transmitting side, one source inputted cross-point switch can be fan-out to multi sources to activate device under test, and different signal trace or length of cables can change phases between multi sources. At the receiving side, all output channels are connected to another RF switch controlled to choose output channel. These two switches both are controlled by software. Multi channels working together will help evaluating cross talk between channels and SSN noise test. In this paper, to ensure test accuracy, signal integrity of DUT and test system is designed and simulated. And an 8-channel optical transceiver is tested using this method and cross talk and power noise are especially showed and analyzed. The test results indicate this test method can meet parallel optical transmission test requirement and other optical module and electrical module test; however the cost is greatly lower than high speed test instruments.