Halil Kukner

Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM

Despite a number of recent advances made in understanding bias temperature instability (BTI), there is still no simple simulation methodology available which can capture the impact of BTI degradation on deeply scaled transistors, while incorporating the widely distributed defect parameters. We present a physics-based defect-controlled methodology for projecting defect property distributions into circuit lifetime and performance distributions. This methodology allows evaluating the entire population of traps (from fast to slow recoverable and permanent traps), which results in faster simulation and proper extrapolation towards long operating lifetimes.

Bias Temperature Instability analysis of FinFET based SRAM cells

Bias Temperature Instability (BTI) is posing a major reliability challenge for todays and future semiconductor devices as it degrades their performance. This paper provides a comprehensive BTI impact analysis, in terms of time-dependent degradation, of FinFET based SRAM cell. The evaluation metrics are read Static Noise Margin (SNM), hold SNM and Write Trip Point (WTP); while the aspects investigated include BTI impact dependence on the supply voltage, cell strength, and design styles (6 versus 8 Transistors cell). A comparison between FinFET and planar CMOS based SRAM cells degradation is also covered. The simulation performed on FinFET based cells for 108 seconds of operation under nominal Vdd show that Read SNM degradation is 16.72%, which is 1.17× faster than hold SNM, while WTP improves by 6.82%. In addition, a supply voltage increment of 25% reduces the Read SNM degradation by 40%, while strengthening the cell pull-down transistors by 1.5× reduces the degradation by only 22%. Moreover, the results reveal that 8T cell degrades 1.31× faster than 6T cell, and that FinFET cells are more vulnerable (~2×) to BTI degradation than planar CMOS cells.

Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution.

BTI impact on logical gates in nano-scale CMOS technology

As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors- has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of inputs duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact.

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology

Reliability of advanced deeply scaled CMOS technologies is being threatened by time-dependent degradation mechanisms such as Negative Bias Temperature Instability (NBTI) phenomenon that cause workload-dependent shifts on a transistors threshold voltage (Vth), and performance during its lifetime. In this study, NBTI related performance degradation of datapath logic subblocks (i.e. adder, multiplier, shifter, mux-demux) are investigated in relation to workload dependency, and architectural topology at 10nm FinFET technology. A workload-dependent, NBTI aging-aware digital design flow was developed within the industry standard EDA tool chain. NBTI model is based on the measured Capture and Emission Time (CET) maps, and scaled to 10nm node. Static Timing Analysis (STA) is performed to evaluate the performance degradation at 3σ corner. Results on datapath subblocks under NBTI aging after 3 years show a performance loss up to 16.7%. NBTI aging results in the replacement of the time-zero critical path by a non-critical path during a circuits lifetime, and it can be significantly high as 91%. Finally, the correlation between aging sensitivity to workload variations, and architectural parameters are shown, and it can vary 12×, and 9×, respectively.

Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation—Application to 6T SRAM

Recent advances in understanding Bias Temperature Instability (BTI) in terms of individual gate oxide defects has created a paradigm shift towards describing degradation in terms of time-dependent variability. This added time dimension to the variability analysis has proven to be a considerable design challenge. Moreover, the non-normally distributed ΔVTH shifts create compatibility issues with the current SotA statistical assessments techniques for evaluating high sigma yield of SRAM cells. Here we present a novel Non-Monte-Carlo numerical simulation methodology capable of evaluating circuit performance under workload-dependent BTI degradation.

Generic, orthogonal and low-cost March Element based memory BIST

This paper contributes to the field of MBIST architecture and implementation by addressing the two most area-critical components: the Command Memory (ComMem) and the Address Generator (AddrGen). The ComMem area is minimized by using a novel MBIST architecture, based on the Generic March Element (GME) concept. A GME is a March Element which specifies the required operations and the generic data values; it can be specified independent of the algorithm stresses. The AddrGen area is minimized by using an efficient implementation, based on a single Up-counter and a set of multiplexors. The experimental results show that the proposed MBIST outperforms the existing MBISTs in terms of area, power, speed, and flexibility. E.g., for a 16Kx16-bit memory, the proposed MBIST consumes about 40% less area and operates at least 1.6 times faster than the state-of-the art.

Scaling of BTI reliability in presence of time-zero variability

In this paper, we first outline the impact of Bias Temperature Instability (BTI) on the transistor threshold voltage as a function of time and the gate oxide field. Subsequently, the correlation between time-zero and time-dependent variability is described. A combined distribution encompassing both contributions with their relative weights is derived. Finally, circuit-level insights on the BTI impact are given based on case study simulations of Ring Oscillators (ROs) at commercial-grade 28nm planar and research-grade 14, 10, 7nm FinFET technology nodes for several FET channel materials (e.g. Si, SiGe, Ge, InGaAs).

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier

With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). A lot of work is published on the impact of BTI in SRAMs; however most of the work focused mainly on the memory cell array. An SRAM consists also of peripheral circuitries such as address decoders, sense amplifiers, etc. This paper characterizes the combined impact of BTI and voltage temperature fluctuations on the memory sense amplifier for different technology nodes (45nm up to 16nm). The evaluation metric, the sensing delay (SD), is analyzed for various workloads. In contrast to earlier work, this paper thoroughly quantifies the increased impact of BTI in such sense amplifiers for all the relevant technology scaling parameters. The results show that the BTI impact for nominal voltage and temperature is 6.7% for 45nm and 12.0% for 16nm when applying the worst case workload, while this is 1.8% for 45nm technology and 3.6% higher for 16nm when applying the best case workload. In addition, the results show that the increase in power supply significantly reduces the BTI degradation; e.g., the degradation at -10%Vdd is 9.0%, while this does not exceed 5.3% at +10%Vdd at room temperature. Moreover, the results that the increase in temperature can double the degradation; for instance, the degradation at room temperature and nominal Vdd is 6.7% while this goes up to 18.5% at 398K.

Incorporating parameter variations in BTI impact on nano-scale logical gates analysis

As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) became a major threat to reliability of CMOS circuits. This threat may even be more severe in the presence of parameter variations such as temperature and process. This paper presents simulation based analysis of BTI and parameter variations in logic gates. Delay, static and dynamic power consumptions are the metrics considered in the analysis. The simulation results show that while considering BTI only, the impact on delay is strongly temperature and duty cycle dependent. For example, in a NOR gate the delay at 75°C and 50% duty cycle is 56% higher than at 25°C; and at 40% duty cycle is 67% higher than at 60%. The results also show that BTI reduced the static and dynamic power. The analysis is redone for BTI by incorporating parameter variation. Monte Carlo simulation results reveal that BTI impact is exacerbated in the presence of parameter variations with up to 15%.