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Dive into the research topics where Hamed Chaabouni is active.

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Featured researches published by Hamed Chaabouni.


international electron devices meeting | 2010

Investigation on TSV impact on 65nm CMOS devices and circuits

Hamed Chaabouni; Maxime Rousseau; P. Leduc; A. Farcy; R. El Farhane; Aurélie Thuaire; G. Haury; Alexandre Valentian; G. Billiot; Myriam Assous; F. De Crecy; J. Cluzel; A. Toffoli; L. Cadix; T. Lacrevaz; Pascal Ancey; N. Sillon; B. Flechet

4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7µA/µm on the static NMOS drain current. However, the ring oscillators response is not impacted.


218th ECS Meeting | 2010

Integration and frequency dependent parametric modeling of Through Silicon Via involved in high density 3D chip stacking

Lionel Cadix; Christine Fuchs; Maxime Rousseau; Patrick Leduc; Hamed Chaabouni; Aurélie Thuaire; M. Brocard; Alexandre Valentian; A. Farcy; Cedric Bermond; Nicolas Sillon; Pascal Ancey; B. Flechet

Evaluation of Through Silicon Via (TSV) electrical performance is hardly required today to improve heterogeneous 3D chip performance in the frame of a “more than Moore” approach. Accurate modeling of TSV is consequently essential to perform design optimizations and process tuning. This paper proposes a methodology based on RF characterizations and simulations, leading to a frequency dependent analytical model including MOS effect of high aspect ratio TSV. Specific test structures integrated on both floating Si bulk and CMOS 65 nm active wafers according to a face-to-face Via Last After Bonding process enable C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) and implemented in SPICE simulator to predict TSV impact on signal propagation.


workshop on signal propagation on interconnects | 2008

Impact of ULK restoration techniques on propagation performance for interconnects of the 45 nm technology node and below

M. Gallitre; Benjamin Blampey; Hamed Chaabouni; A. Farcy; P. Grosgeorges; T. Lacrevaz; C. Bermond; B. Flechet; Pascal Ancey

The development of advanced ICs architectures for the 45 nm technology node and beyond faces several integration and performance issues. Porous dielectrics are very prone to degradation during process flow, potentially compromising signal integrity. Specific processes such as annealing, restoration treatments, and pore-sealing by liner deposition are considered as potential solutions. Their utility and impact on propagation performance is investigated through both RF measurements and electromagnetic simulations.


Archive | 2010

Electrical connection via for the substrate of a semiconductor device

Hamed Chaabouni; Lionel Cadix


Archive | 2011

ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS

Yacine Felk; Hamed Chaabouni; A. Farcy


Archive | 2010

ELECTRIC VIA COMPRISING LATERAL OUTGROWTHS

Hamed Chaabouni; Lionel Cadix


Archive | 2010

SCALLOPED TUBULAR ELECTRIC VIA

Hamed Chaabouni; Lionel Cadix


Archive | 2010

Electrical via with lateral extensions

Hamed Chaabouni; Lionel Cadix


Archive | 2010

Electric via with a rough lateral surface

Hamed Chaabouni; Lionel Cadix


Archive | 2013

Tubular electrical via consisting of a plurality of elementary conductive vias

Hamed Chaabouni; Lionel Cadix

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