Pedro Toledo

Self-biased CMOS Current Reference based on the ZTC Operation Condition

A self-biased current reference based on the MOSFET Zero Temperature Coefficient (ZTC) condition is presented. It can be implemented in any CMOS process and it provides a simple alternative to design a reference current suitable for low TC biasing. This topology was designed in a 0.18 μm process to generate 5 μA under a supply voltage from 1.4V to 1.8 V, spending a silicon area around 0.010mm2. From circuit simulations, the current reference is estimated to have a temperature coefficient (TCeff ) of 15 ppm/°C from -40 to +85 °C and a fabrication sensitivity of σ/μ = 4.5%, including average process and local mismatch variability. The power supply sensitivity resulted around 1%V for this new reference.

A Low-Voltage Current Reference with High Immunity to EMI

An electromagnetic interference (EMI) source can significantly degrade the performance of a current reference since its finite Power Supply Rejection Ratio (PSRR) of the later. For that reason A modified current reference with high immunity to EMI and a new current mirror structure insensitive to induced EMI are proposed based on the classic boot-strapped current and compared to other current reference structures. Simulations results using XFAB 0.18 μm CMOS process demonstrate the high immunity to EMI of the proposed current reference. Improvements in the PSRR of 48dB and 32dB in comparison to the classical version and other implementations respectively.

A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero- V T active loads

A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is presented. The voltage reference is generated from the threshold voltage (VT) difference of two transistors biased in weak inversion. The VT difference is achieved through its dependence with the transistor dimensions. The high-PSRR is obtained using zero-VT transistors as active loads. The final circuit was designed in a 130 nm CMOS process and occupies around 0.0007 mm2 of silicon area while consuming just 18.5 pW at 27°C. Post-layout simulations present a 62 mV reference voltage with a temperature coefficient of 15 ppm/°C, for a temperature range from -25 to 125 °C and a Power Supply Rejection Ratio (PSRR) of -68.7 dB at 0.3 V of supply voltage.

Resistorless switched-capacitor current reference based on the MOSFET ZTC condition

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 μA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TCeff ) of 60 ppm/°C from -45 to +85 °C and a power consumption of 63 μW.

A 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference

Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from -55 to 125 ° C. An EMI source of 4 dBm (1 Vpp) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 μVpp, respectively.

CMOS Transconductor Analysis for Low Temperature Sensitivity Based on ZTC MOSFET Condition

The necessary conditions to design MOSFET transconductors with low temperature dependence are analysed and defined in this paper. Transconductors, or Gm circuits, are fundamental blocks used to implement adjustable filters, multipliers, controlled oscillators, amplifiers and a large variety of analog circuits. Temperature stability is a must in such applications, and herein we show a strategy that can be used to improve the temperature stability of these transconductors by biasing MOSFETs at transconductance zero-temperature condition (GZTC). This special bias condition is analysed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are proposed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits were simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

0.5 V Supply Voltage Reference Based on the MOSFET ZTC Condition

The continuous scaling of CMOS devices has required the consequent reduction of the supply voltages. There is a need for analog and RF circuits able to operate under at supplies lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is composed by a diode-connected MOS transistor operating near the ZTC condition that is biased by a proportional-to-absolute-temperature (PTAT) current reference implemented with Schottky-diodes. The ZTC condition is analysed using a continuous MOSFET model that is valid from weak to strong inversion and the circuit behaviour is described by theoretical expressions. Our reference circuit is designed for 3 versions: each with MOSFETs of different threshold voltage (standard-VT, low-VT, and zero-VT), all available in the 130 nm CMOS process used. These designs result in three different and very low reference voltages: 312, 237, and 51 mV. All 3 designed reference operate in the range of 0.45 to 1.2 V of supply voltages, consuming 1 uA of typical supply current. Post-layout simulations present a Temperature Coefficients (TCs) of 214, 372, and 953 ppm/°C in a temperature range from -55 to 125°C, respectively. Monte-Carlo simulations show the fabrication variability impact on the circuit performance. The voltage reference was designed in a 130 nm process and it uses 0.014 mm2 of silicon area.

Low power IEEE 802.11ah receiver system-level design aiming for IoT applications

Internet of Things (IoT) is a topic of growing interest and intensive research in industry, technological centers and academy, where data communication is one of its most relevant aspects. Since IoT is an open field for new applications, it does not have yet a standard communication protocol. This paper presents the system level design of a WiFi receiver supporting the novel low power standard IEEE 802.11ah with focus on IoT applications. Theoretical performance analysis as well as system level design strategies are presented. Individual blocks of the receiver chain are specified as a condition for future circuit-level design. Simulation results validate the proposed system specifications attending the 802.11ah standard. The presented receiver provides 80.5dB maximum gain, 9 dB minimum noise figure and 69.4 dB of dynamic range. Those performance parameters lead to −99.4 dBm sensitivity, 21 dB and 51 dB for adjacent and non-adjacent maximum channel rejection.

A sub-1 V, nanopower, ZTC based zero-VT temperature-compensated current reference

A nano-ampere current reference with temperature compensation operating is presented. The reference current is generated biasing a zero-VT transistor near its Zero-temperature coefficient (ZTC) point. Two versions were implemented in a 180 nm CMOS process. Both are designed using the same thermal compensation principle, but the second version uses an auxiliary circuit to compensate process variation. The circuits occupy 0.01 and 0.018 mm2 of silicon area while consuming around 30.5 and 122 nW at 27° C, respectively. Post-layout simulations present a reference current of 10.86 and 10.95 nA with a average temperature coefficient of 108 and 127 ppm/°C (100 Samples), under a temperature range from −20 to 120 °C, and a line sensitivity of 0.54 and 0.86 %/V at 0.9 V to 1.8 V of supply voltage, respectively.

A 0.7V fully differential first order GZTC-C filter

A 0.7 V supply voltage fully differential first order GZTC-C filter is herein proposed. The GZTC-C filter definition is used in this paper as a Transconductance-Capacitor filter (Gm-C) in which its gm stage is biased exactly on transconductance zero-temperature (GZTC) bias condition. This special bias point has all necessary conditions to design MOSFET transconductors with low temperature dependence. Additionally, two calibrate-points with three-bit resolution have been added to mitigate process variations which may cause bias shift errors on sensitive nodes, driving the circuit out of its normal GZTC operation region. The final circuit has been designed in a 130 nm CMOS process generating a 5 MHz cutoff frequency. The filter occupies around 0.01 mm2 of silicon area while consuming just 21 μW. Monte Carlo (MC) post-layout and post-calibrated simulation has presented an Effective Cutoff Frequency Temperature Co-efficient (TCeff) average of 73.4 ppm/°C with 30.6 ppm/°C standard deviation for a temperature range from -40 to +120°C and has estimated a cutoff frequency fabrication sensitivity of σ/μ = 0.87%, including average process and local mismatch variability.