Hanju Oh

Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems

Microfluidic cooling shows promise in cooling next generation 3D microsystems when integrated with through-silicon-vias. In this work, electrical and thermal effects of staggered micropin-fin heat sink dimensions are analyzed using deionized water. An experimental study of five different silicon micropin-fin arrays with a nominal height of 200 μm and diameters down to 30 μm was conducted at flow rates up to approximately 100mL/min and pressure drops up to approximately 200 kPa. The lowest convective thermal resistance achieved was 0.098 °C/W across a 1 cm2 die. These experimental results were then used to simulate temperature profiles of an interposer-cooled 3D stack.

In-situ microscale through-silicon via strain measurements by synchrotron x-ray microdiffraction exploring the physics behind data interpretation

In-situ microscale thermomechanical strain measurements have been performed in combination with synchrotron x-ray microdiffraction to understand the fundamental cause of failures in microelectronics devices with through-silicon vias. The physics behind the raster scan and data analysis of the measured strain distribution maps is explored utilizing the energies of indexed reflections from the measured data and applying them for beam intensity analysis and effective penetration depth determination. Moreover, a statistical analysis is performed for the beam intensity and strain distributions along the beam penetration path to account for the factors affecting peak search and strain refinement procedure.

Low-Loss Air-Isolated Through-Silicon Vias for Silicon Interposers

An air-isolated through-silicon via (TSV) technique is proposed to reduce radio-frequency (RF) losses in silicon interposers. A testbed containing air-isolated and conventional TSVs is fabricated and characterized from 10 MHz to 20 GHz with an L-2L de-embedding technique. The proposed air-isolated TSV technique yields 46.7% lower insertion loss compared to conventional TSVs at 20 GHz from 3-D full-wave simulations and measurements. Moreover, the impact of the air-isolation region width between TSVs on capacitance and conductance is quantified.

Silicon interposer platform with low-loss through-silicon vias using air

A silicon interposer platform featuring low-loss through-silicon vias (TSVs) using air is proposed and demonstrated. The proposed low-loss TSVs are fabricated by partially etching silicon between the signal and ground TSVs. High-frequency characterization in the 10 MHz-to-20 GHz frequency range demonstrates that the proposed TSVs reduce capacitance by 63.2% at 20 GHz compared to conventional TSVs.

Analysis of Signal Propagation Through TSVs Within Distilled Water for Liquid-Cooled Microsystems

This paper analyzes the impact of liquid cooling on the electrical characteristics of through-silicon vias (TSVs) using a microfluidic cooling testbed containing TSVs. The microfabrication of TSVs in a silicon micropin-fin heat sink is presented, and the high-frequency characterization of TSVs within a micropin-fin heat sink using distilled water is performed from 10 MHz to 20 GHz. TSV capacitance and conductance are extracted from measurements; TSVs within distilled water have larger capacitance and conductance than TSVs in silicon due to the lossy characteristics of distilled water at high frequencies. A coaxial-like TSV configuration, which consists of multiple ground TSVs surrounding a center signal TSV, is proposed and demonstrated to shield signal TSVs from the coolant.

Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits With Through-Silicon Vias: Part II

3-D integration using through-silicon vias (TSVs) can decrease interconnect length and improve chip performance. In this paper, electrical links consisting of TSVs and horizontal wires are designed, fabricated, and measured to analyze TSV capacitance and link delay. Compact models for the capacitance of a TSV surrounded by variable number of ground TSVs are developed and compared with measurements. The impact of TSV placement and scaling on link performance is further analyzed. The results demonstrate that placing TSVs closer to their drivers can effectively improve the performance of 3-D integrated circuit (3-D IC) links. Moreover, link delay is significantly improved by scaling TSV geometry to the point that 3-D IC links become on-chip wire limited.

Fabrication and Characterization of Electrical Interconnects and Microfluidic Cooling for 3D ICS With Silicon Interposer

Heat generation in high-performance three-dimensional integrated circuits (3D ICs) is a significant challenge due to limited heat removal paths and high power density. To address this challenge, this paper presents an embedded microfluidic heat sink (MFHS) for such high-performance 3D ICs. In the proposed 3D IC system, each tier contains an embedded MFHS, along with high-aspect-ratio (23:1) through-silicon vias (TSVs) routed through the MFHS. In each tier, solder-based electrical and fluidic inputs/outputs are co-fabricated with wafer-level batch fabrication. Moreover, microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time.

High-Frequency Analysis of Embedded Microfluidic Cooling within 3-D ICs Using a TSV Testbed

In this paper, the impact of microfluidic cooling on the electrical characteristics of through-silicon vias (TSVs) is investigated for three-dimensional (3-D) integrated circuits (ICs). The design and fabrication of a testbed containing TSVs are presented for two types of heat sinks (micropin-fin and microchannel heat sinks) immersed in deionized (DI) water. The high-frequency characterization of TSVs in the DI water-filled testbed is performed and compared to conventional TSVs in silicon. TSVs in DI water demonstrate higher insertion loss, capacitance, and conductance than TSVs in silicon. In this paper, we also present coaxially shielded TSVs embedded in a pin-fin heat sink and demonstrate the electrical isolation of the signal TSV from the surrounding DI water.

Electrical Interconnect and Microfluidic Cooling Within 3D ICs and Silicon Interposer

Heat dissipation is a significant challenge for three-dimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solder-based microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters.Copyright

Monolithic-like heterogeneously integrated microsystems using dense low-loss interconnects

In this paper, two integration technologies are discussed for heterogeneously integrated microsystems. First, this paper presents low-loss TSVs using an air-isolation technique for silicon interposers. The proposed air-isolated TSVs exhibit approximately 35% and 37% reduction in insertion loss and capacitance, respectively, at 20 GHz. Moreover, this paper presents a TSV-less integration technology using bridge chips and Compressible MicroInterconnects (CMIs). Compared to other packaging and assembly options, the investigated TSV-less approach provides monolithic-like electrical performance by significantly reducing chip-to-chip interconnect length and loss, increasing interconnect density, and providing the ability to seamlessly integrate chips of diverse functionalities.