Xuchen Zhang

A Review of Two-Phase Forced Cooling in Three-Dimensional Stacked Electronics: Technology Integration

Three-dimensional (3D) stacked electronics present significant advantages from an electrical design perspective, ranging from shorter interconnect lengths to enabling heterogeneous integration. However, multitier stacking exacerbates an already difficult thermal problem. Localized hotspots within individual tiers can provide an additional challenge when the high heat flux region is buried within the stack. Numerous investigations have been launched in the previous decade seeking to develop cooling solutions that can be integrated within the 3D stack, allowing the cooling to scale with the number of tiers in the system. Two-phase cooling is of particular interest, because the associated reduced flow rates may allow reduction in pumping power, and the saturated temperature condition of the coolant may offer enhanced device temperature uniformity. This paper presents a review of the advances in two-phase forced cooling in the past decade, with a focus on the challenges of integrating the technology in high heat flux 3D systems. A holistic approach is applied, considering not only the thermal performance of standalone cooling strategies but also coolant selection, fluidic routing, packaging, and system reliability. Finally, a cohesive approach to thermal design of an evaporative cooling based heat sink developed by the authors is presented, taking into account all of the integration considerations discussed previously. The thermal design seeks to achieve the dissipation of very large (in excess of 500 W/cm2) background heat fluxes over a large 1 cm × 1 cm chip area, as well as extreme (in excess of 2 kW/cm2) hotspot heat fluxes over small 200 μm × 200 μm areas, employing a hybrid design strategy that combines a micropin–fin heat sink for background cooling as well as localized, ultrathin microgaps for hotspot cooling.

3D IC With Embedded Microfluidic Cooling: Technology, Thermal Performance, and Electrical Implications

In this paper, a novel thermal testbed with an embedded micropin-fin heat sink is designed and fabricated. The micropin-fin array has a nominal height of 200 μm and a diameter of 90 μm. Single phase and two phase thermal testing of the micropin-fin array heat sink are performed using deionized (D.I.) water as the coolant below atmospheric pressure. The measured pressure drop is as high as 100 kPa with a mass flux of 1637 kg/m2s at a heat flux of 400 W/cm2 in a two-phase regime. The heat transfer coefficient and the vapor quality are calculated and reported. The impact of microfluidic cooling on the electrical performance of the 3D interconnects is also analyzed. The high aspect ratio through silicon vias (TSVs) used in the electrical analysis have a nominal diameter of 10 μm.© 2015 ASME

Flow boiling of R245fa in a microgap with integrated staggered pin fins

We present an experimental study of two phase flow of refrigerant R245fa in a pin fin enhanced microgap for a range of heat fluxes between 151 W/cm2 to 326 W/cm2. The gap has a base surface area of 1cm × 1cm and height of 200 μm. An array of hydrofoil shaped pin fins covers from bottom to top of the microgap. The pin fins have chord length, longitudinal pitch, and transversal pitch of 75μm, 450μm and 225μm, respectively. On the back side of the chip, four platinum heaters are fabricated and electrically powered in series to enable two phase flow in the microgap, which was part of a pumped flow loop. Heater and surface temperature data were obtained versus heat flux dissipated. Flow visualization was performed using a high speed camera in the heat flux range from 151 W/cm2 to 326 W/cm2. The amount of heat loss across the test section is also provided.

Three-Dimensional Integrated Circuit With Embedded Microfluidic Cooling: Technology, Thermal Performance, and Electrical Implications

This paper reports on novel thermal testbeds with embedded micropin-fin heat sinks that were designed and microfabricated in silicon. Two micropin-fin arrays were presented, each with a nominal pin height of 200 lm and pin diameters of 90 lm and 30 lm. Singlephase and two-phase thermal testing of the micropin-fin array heat sinks were performed using de-ionized (DI) water as the coolant. The tested mass flow rate was 0.001 kg/s, and heat flux ranged from 30 W/cm to 470 W/cm. The maximum heat transfer coefficient reached was 60 kW/m K. The results obtained from the two testbeds were compared and analyzed, showing that density of the micropin-fins has a significant impact on thermal performance. The convective thermal resistance in the single-phase region was calculated and fitted to an empirical model. The model was then used to explore the tradeoff between the electrical and thermal performance in heat sink design. [DOI: 10.1115/1.4032496]

Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits With Through-Silicon Vias: Part II

3-D integration using through-silicon vias (TSVs) can decrease interconnect length and improve chip performance. In this paper, electrical links consisting of TSVs and horizontal wires are designed, fabricated, and measured to analyze TSV capacitance and link delay. Compact models for the capacitance of a TSV surrounded by variable number of ground TSVs are developed and compared with measurements. The impact of TSV placement and scaling on link performance is further analyzed. The results demonstrate that placing TSVs closer to their drivers can effectively improve the performance of 3-D integrated circuit (3-D IC) links. Moreover, link delay is significantly improved by scaling TSV geometry to the point that 3-D IC links become on-chip wire limited.

Flow visualization of two phase flow of R245fa in a microgap with integrated staggered pin fins

We have visualized two phase flow cooling of R245fa refrigerant in a 1 cm × 1 cm × 200 μm microgap, equipped with circular pin-fins. The device has the microgap with sparse circular pin-fin arrangement of transverse pitch, longitudinal pitch, and pin-fin diameter of 225 μm, 225 μm, and 75 μm, respectively. On the back side of the chip, four integrated platinum heaters are fabricated and are arranged in series. The microgap is installed in a closed flow loop that is pressurized. The inlet flow is subcooled at the elevated pressure. Flow boiling is obtained in the microgap for a range of heat flux values between 7 W/cm2 to 34 W/cm2. Using a high speed camera, flow visualization results are presented for the range of heat flux values.

Silicon interposer with embedded microfluidic cooling for high-performance computing systems

A silicon interposer platform utilizing microfluidic cooling is proposed to address the off-chip signaling and cooling challenges facing future high-performance computing systems. A test vehicle with microfluidic I/Os and a micropin-fin heat sink was used to evaluate microfluidic cooling performance. De-ionized water (~20 °C) was used as the coolant. At a flow rate of 50 mL/min, the measured temperature was 55.9 °C for a power density of 97.0 W/cm2. Compared to air cooling, microfluidic cooling significantly improves cooling performance and thermal isolation. Moreover, 3-D integration of two silicon dice with microfluidic I/Os on a silicon interposer is demonstrated.

Reliability assessment of hydrofoil-shaped micro-pin fins

As the need for high performance and extreme power-dissipation microelectronic devices continues to rise, innovative thermal management solutions are being developed to efficiently remove the high heat fluxes dissipated in these applications. At heat flux rates surpassing the 1000 W/cm2 level in some localized hot spot cases, conductive spreading to an external heat sink is no longer a viable thermal management option. On-chip, enhanced microfluidic cooling with pin fins offers new opportunities to deliver coolant in close proximity to power dissipation zones and hot spots. In state-of-the-art designs a two-phase refrigerant is pumped through a microfluidic channel within an active device absorbing heat at high velocity. Hydrofoil-shaped, silicon micro-pin fins populate the flow space to increase surface area available for heat removal and for liquid films to coalesce. The proposed thermal-management system has been fabricated by etching the microchannel with hydrofoil pin fins into the backside of the silicon device and then bonding it to a capping layer. While the hydrofoil shape is designed to benefit thermal-fluid performance properties, reliability consideration must also be given to the geometry. Phase change of the liquid facilitates optimal heat removal rates but also requires high-pressure conditions for operation. At these high-pressure conditions, the pin fins will be subjected to stress due to fluid pressure. Because of the unique geometry of the hydrofoil pin fins, special consideration must be given to the interaction of stress concentrations due to fluidic pressure loading and the small radius of curvature of the hydrofoil tail. The objective of this paper is to examine the various sources of stress in this high-performance, micro-pin fin channel and explore the reliability of this hydrofoil pin fin design under high-pressure conditions.

High-Frequency Analysis of Embedded Microfluidic Cooling within 3-D ICs Using a TSV Testbed

In this paper, the impact of microfluidic cooling on the electrical characteristics of through-silicon vias (TSVs) is investigated for three-dimensional (3-D) integrated circuits (ICs). The design and fabrication of a testbed containing TSVs are presented for two types of heat sinks (micropin-fin and microchannel heat sinks) immersed in deionized (DI) water. The high-frequency characterization of TSVs in the DI water-filled testbed is performed and compared to conventional TSVs in silicon. TSVs in DI water demonstrate higher insertion loss, capacitance, and conductance than TSVs in silicon. In this paper, we also present coaxially shielded TSVs embedded in a pin-fin heat sink and demonstrate the electrical isolation of the signal TSV from the surrounding DI water.

Monolithic-like heterogeneously integrated microsystems using dense low-loss interconnects

In this paper, two integration technologies are discussed for heterogeneously integrated microsystems. First, this paper presents low-loss TSVs using an air-isolation technique for silicon interposers. The proposed air-isolated TSVs exhibit approximately 35% and 37% reduction in insertion loss and capacitance, respectively, at 20 GHz. Moreover, this paper presents a TSV-less integration technology using bridge chips and Compressible MicroInterconnects (CMIs). Compared to other packaging and assembly options, the investigated TSV-less approach provides monolithic-like electrical performance by significantly reducing chip-to-chip interconnect length and loss, increasing interconnect density, and providing the ability to seamlessly integrate chips of diverse functionalities.