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Dive into the research topics where Masataka Miyake is active.

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Featured researches published by Masataka Miyake.


IEEE Transactions on Electron Devices | 2006

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

Mitiko Miura-Mattausch; Norio Sadachika; Dondee Navarro; G. Suzuki; Youichi Takeda; Masataka Miyake; Tomoyuki Warabino; Yoshio Mizukane; Ryosuke Inagaki; Tatsuya Ezaki; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; Shigetaka Kumashiro; S. Miyamoto

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics


IEEE Transactions on Electron Devices | 2006

A Carrier-Transit-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application to Harmonic Distortion Analysis

Dondee Navarro; Youichi Takeda; Masataka Miyake; Noriaki Nakayama; Ken Machida; Tatsuya Ezaki; Hans Jürgen Mattausch; Mitiko Miura-Mattausch

In this paper, a compact model of nonquasi-static (NQS) carrier-transport effects in MOSFETs is reported, which takes into account the carrier-response delay to form the channel. The NQS model, as implemented in the surface-potential-based MOSFET Hiroshima University STARC IGFET model, is verified to predict the correct transient terminal currents and to achieve a stable circuit simulation. Simulation results show that the NQS model can even reduce the circuit simulation time in some cases due to the elimination of unphysical overshoot peaks normally calculated by a QS-model. An average additional computational cost of only 3% is demonstrated for common test circuits. Furthermore, harmonic distortion characteristics are investigated using the developed NQS model. While the distortion characteristics at low drain bias and low switching frequency are determined mainly by carrier mobility, distortion characteristics at high frequency are found to be strongly influenced by channel charging/discharging


IEEE Transactions on Electron Devices | 2010

HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits

Y. Oritsuki; M. Yokomichi; T. Kajiwara; Akihiro Tanaka; Norio Sadachika; Masataka Miyake; Hideyuki Kikuchihara; Koh Johguchi; Uwe Feldmann; Hans Jürgen Mattausch; Mitiko Miura-Mattausch

The completely surface-potential-based MOSFET model HiSIM-HV for high-voltage applications of up to several hundred volts is reviewed, and recently developed new model capabilities are presented. HiSIM-HV enables a consistent evaluation of current and capacitance characteristics for symmetric and asymmetric high-voltage MOSFETs due to a consistent description of the potential distribution across the MOSFET channel as well as the resistive drift regions. The anomalous features, often observed in the capacitances, are explained by large potential drops in the drift regions. Accurate modeling of the overlap region between the gate and drift region is also demonstrated. Different device features based on different device structures are well explained by the geometrical differences.


IEEE Transactions on Electron Devices | 2011

Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices

Akihiro Tanaka; Y. Oritsuki; Hideyuki Kikuchihara; Masataka Miyake; Hans Jürgen Mattausch; Mitiko Miura-Mattausch; Yong Liu; Keith Green

High-voltage (HV) metal-oxide-semiconductor field-effect transistors (MOSFETs) of the laterally diffused metal-oxide-semiconductor (LDMOS) type enable applications over a wide range of bias voltages by optimizing the combined structure of MOSFET and drift region at its drain side. We report a physically accurate compact resistor model of the LDMOS drift region, adapted to the special requirements of the combined structure with a MOSFET. In particular, the reported resistor model captures the effects of the 2-D current flow in the drift region with its complicated bias dependence. The resistor model considers two device-structure-dependent potentials, namely, the internal node potential within the highly resistive drift region and the potential underneath the gate overlap region. The consistent potential-based description over the complete LDMOS device is the key modeling technology for enabling the accurate reproduction of the bias-dependent 2-D current flow and the resulting I-V characteristics for a wide range of structure variations with a small number of only six fitting parameters. The reported quasi-2-D resistor model is implemented in the second-generation Hiroshima-university STARC IGFET Model-High Voltage (HiSIM-HV) compact models for HV MOSFETs and is expected to be useful for both, optimization of LDMOS circuits and devices.


Japanese Journal of Applied Physics | 2008

Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization

M. Yokomichi; Norio Sadachika; Masataka Miyake; T. Kajiwara; Hans Jürgen Mattausch; Mitiko Miura-Mattausch

A laterally diffused metal oxide semiconductor (LDMOS) device enables the realization of a wide range of application voltages by varying impurity concentration and the length of the lightly doped drain contact region. However, this resistive contact region causes the abnormal characteristics observed in capacitances. Here, the HiSIM-LDMOS model based on a complete surface-potential description is demonstrated, which simulates the features of the LDMOS device consistently. With this model, an optimization scheme for the LDMOS device for requested features is discussed.


international reliability physics symposium | 2013

Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation

Chenyue Ma; Hans Jürgen Mattausch; Masataka Miyake; Takahiro Iizuka; M. Miura-Mattausch; Kazuya Matsuzawa; Seiichiro Yamaguchi; Teruhiko Hoshida; Masahiro Imade; Risho Koh; Takahiko Arakawa; Jin He

A compact reliability model is reported, which includes both the channel hot carrier (CHC) and the negative bias thermal instability (NBTI) effects in p-MOSFETs. The developed compact NBTI model, which describes both interface-state generation and hole-trapping mechanisms, is further improved by considering additionally the impact of the drain bias Vds. With increased Vds, the NBTI effect is weakened due to the reduction of the vertical gate oxide field, and the CHC effect is enhanced by the increased lateral channel electric field. Therefore, the threshold voltage is observed to decrease in the low Vds regime, and then increases again in the high Vds regime. Such “turn-around” characteristic is correctly modeled using the improved compact NBTI model. Implementation of this reliability model into the surface-potential-based compact model HiSIM enables accurate prediction of the CHC enhanced NBTI degradation for wide ranges of time duration and bias conditions. This allows real-time simulation for the circuit-performance degradation occurring during actual circuit operation.


power electronics specialists conference | 2008

A consistently potential distribution oriented compact IGBT model

Masataka Miyake; A. Ohashi; M. Yokomichi; H. Masuoka; T. Kajiwara; Norio Sadachika; Uwe Feldmann; Hans Jürgen Mattausch; Mitiko Miura-Mattausch; Takashi Kojima; T. Shoji; Yuji Nishibe

With the trend to higher switching speed for IGBTs, the dynamics of the MOS part have increasing impact on device characteristics. In addition, the base-charge distribution of the BJT part has also to be modeled quite accurately to capture the IGBTs overall dynamic behavior adequately. We present a new IGBT model for circuit simulation, where all controlling potentials in the base region are calculated under fully dynamic load conditions, and which includes an advanced surface- potential-based charge-oriented MOSFET model. The approach assures that the dynamic interaction between MOS and BJT part is accurately taken into account. The models abilities to describe the impact of the MOS-gate capacitance on the IGBT output characteristics, and to capture dynamic effects like overshoot under rapid switch- off conditions, are verified.


IEEE Transactions on Electron Devices | 2013

The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs

Hans Jürgen Mattausch; Masataka Miyake; Takahiro Iizuka; Hideyuki Kikuchihara; Mitiko Miura-Mattausch

This paper reviews the industry-standard surface-potential-based compact model HiSIM_HV for high-voltage MOSFETs, as, e.g., the lateral double-diffused MOS transistor, and introduces important improvements implemented in the second-generation model versions (HiSIM_HV2), for which open source code has been released since October 2011. HiSIM_HV solves the Poisson equation consistently within the intrinsic MOSFET, i.e., the gate-drift overlap region and the drain-side part of the drift region. Excess carrier concentrations in the drift region are accurately considered together with the velocity saturation effect. These modeling concepts enable a scalable compact model formulation with only one internal node. Fulfillment of the current continuity between MOSFET and drift parts is required for determining the internal node potential. An important enhancement implemented in the HiSIM_HV2 models is a physically accurate compact drift region resistance model, which captures the effects of the structure-dependent 2-D current flows in overlap and drift regions with their complicated bias dependence. Furthermore, compact modeling of gate overlap capacitance, leakage currents due to, e.g., impact ionization, self-heating, noise, and symmetry properties (smooth derivatives at zero drain-source voltage) have been substantially improved.


international conference on solid-state and integrated circuits technology | 2008

HiSIM-HV: A compact model for simulation of high-voltage-MOSFET circuits

Hans Jürgen Mattausch; T. Kajiwara; M. Yokomichi; T. Sakuda; Y. Oritsuki; Masataka Miyake; Norio Sadachika; Hideyuki Kikuchihara; Uwe Feldmann; Mitiko Miura-Mattausch

The high-voltage MOSFET model HiSIM-HV is based on the HiSIM (Hiroshima-university STARC IGFET Model) model for conventional bulk MOSFETs [1, 2] and features a consistent potential description across MOSFET channel and drift region. Symmetric and asymmetric device types are covered for up to several 100 V switching capability. Accurate scaling properties for channel and drift-region length as well as channel width are also provided.


IEEE Transactions on Electron Devices | 2013

Modeling of SiC IGBT Turn-Off Behavior Valid for Over 5-kV Circuit Simulation

Masataka Miyake; Masaya Ueno; Uwe Feldmann; Hans Jürgen Mattausch

This paper presents a compact model of SiC insulated-gate bipolar transistors (IGBTs) for power electronic circuit simulation. Here, we focus on the modeling of important specific features in the turn-off characteristics of the 4H-SiC IGBT, which are investigated with a 2-D device simulator, at supply voltages higher than 5 kV. These features are found to originate from the punch-through effect of the SiC IGBT. Thus, they are modeled based on the carrier distribution change caused by punch through and implemented into the silicon IGBT model named “HiSIM-IGBT” to obtain a practically useful SiC-IGBT model. The developed compact SiC-IGBT model for circuit simulation is verified with the 2-D device simulation data.

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