Norio Sadachika

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects

The reported circuit simulation model Hiroshima University semiconductor technology academic research center IGFET model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI-MOSFET is based on a complete surface-potential description. Not only the surface potential in the MOSFET channel, but also the potentials at both surfaces of the buried oxide are solved iteratively, which allows including of all relevant device features of the SOI-MOSFET explicitly and in a physically correct way. In particular, an additional parasitic electric field, induced by the surface-potential distribution at the buried oxide, has to be included for accurate modeling of the short-channel effects. The total iteration time for surface potential calculation with HiSIM-SOI is under most bias conditions only a factor 2.0 (up to a factor 3.0 for some bias conditions) longer than for the bulk-MOSFET HiSIM model, where just the channel surface potential is involved. It is verified that HiSIM-SOI reproduces measured current-voltage (I-V) and 1/f noise characteristics of a 250-nm fully depleted SOI technology in the complete operating range with an average error of 1% and 15%, respectively. Stable convergence of HiSIM-SOI in the circuit simulation is confirmed

HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits

The completely surface-potential-based MOSFET model HiSIM-HV for high-voltage applications of up to several hundred volts is reviewed, and recently developed new model capabilities are presented. HiSIM-HV enables a consistent evaluation of current and capacitance characteristics for symmetric and asymmetric high-voltage MOSFETs due to a consistent description of the potential distribution across the MOSFET channel as well as the resistive drift regions. The anomalous features, often observed in the capacitances, are explained by large potential drops in the drift regions. Accurate modeling of the overlap region between the gate and drift region is also demonstrated. Different device features based on different device structures are well explained by the geometrical differences.

Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization

A laterally diffused metal oxide semiconductor (LDMOS) device enables the realization of a wide range of application voltages by varying impurity concentration and the length of the lightly doped drain contact region. However, this resistive contact region causes the abnormal characteristics observed in capacitances. Here, the HiSIM-LDMOS model based on a complete surface-potential description is demonstrated, which simulates the features of the LDMOS device consistently. With this model, an optimization scheme for the LDMOS device for requested features is discussed.

Complete Surface-Potential-Based Fully-Depleted Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistor Model for Circuit Simulation

The circuit simulation model Hiroshima-university STARC IGFET Model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI metal-oxide-semiconductor field-effect-transistor (MOSFET) is developed based on the surafce-potential description. To include all device features of the SOI-MOSFET explicitly, the surface potential values not only at the SOI surface but also the back side, as well as the bulk back-gate are solved iteratively. The total iteration for the potential calculation requires only about twice as much calculation time as the bulk-MOSFET case, solving ony at the surface. The model reproduces measured I–V characteristics within numerical accuracy, and is proved stable circuit convergence.

A consistently potential distribution oriented compact IGBT model

With the trend to higher switching speed for IGBTs, the dynamics of the MOS part have increasing impact on device characteristics. In addition, the base-charge distribution of the BJT part has also to be modeled quite accurately to capture the IGBTs overall dynamic behavior adequately. We present a new IGBT model for circuit simulation, where all controlling potentials in the base region are calculated under fully dynamic load conditions, and which includes an advanced surface- potential-based charge-oriented MOSFET model. The approach assures that the dynamic interaction between MOS and BJT part is accurately taken into account. The models abilities to describe the impact of the MOS-gate capacitance on the IGBT output characteristics, and to capture dynamic effects like overshoot under rapid switch- off conditions, are verified.

Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model

Variation analysis of n-MOSFETs fabricated by different manufacturers at three technology nodes (180, 100, and 65 nm) demonstrates that surface-potential compact models are capable to bridge the gap between circuit simulation and TCAD by enabling extraction of microscopic MOSFET-parameter variation from measured macroscopic Vth and Ion variations. Considering only the four microscopic variations of substrate doping, pocket-implantation doping, carrier mobility degradation due to gate-interface roughness, and channel-length change, is found sufficient to reproduce within-wafer Vth and Ion variations of wide MOSFETs (Wg = 10 mum) for all Lg and all three technology nodes. Extracted microscopic variation reductions between 180- and 65-nm nodes range from 25% for pocket doping to 70% for carrier mobility degradation. However, Vth and Ion variations at shortest Lg remain approximately constant for all three technologies, in spite of the substantial variation reductions at the microscopic level.

HiSIM-HV: A compact model for simulation of high-voltage-MOSFET circuits

The high-voltage MOSFET model HiSIM-HV is based on the HiSIM (Hiroshima-university STARC IGFET Model) model for conventional bulk MOSFETs [1, 2] and features a consistent potential description across MOSFET channel and drift region. Symmetric and asymmetric device types are covered for up to several 100 V switching capability. Accurate scaling properties for channel and drift-region length as well as channel width are also provided.

Modeling of Floating-Body Effect in Silicon-on-Insulator Metal–Oxide–Silicon Field-Effect Transistor with Complete Surface-Potential-Based Description

In this work, a silicon-on-insulator (SOI) metal–oxide–silicon field-effect transistor (MOSFET) model for circuit simulation is reported, which covers also the floating-body effect induced by the additional charge generated through impact ionization. The model is based on the complete surface-potential description and solves the Poisson equation with inclusion of the impact ionization. The developed compact SOI-MOSFET model is verified to reproduce two-dimensional-device simulation results very well, and shows the characteristic potential increase at the back side of the SOI layer. The steep drain-current (Ids) increase at high drain-voltages (Vds), caused by the floating-body effect, is also accurately captured.

Analysis and Compact Modeling of MOSFET High-Frequency Noise

We have developed a high-frequency noise model for short channel MOSFETs by considering the position dependent surface potential which results in a non-uniform mobility distribution along the channel. The chosen approach successfully reproduces the induced-gate noise and the cross-correlation noise between drain and gate for short channel MOSFETs without additional model parameters. In particular, the gate noise characteristics at GHz frequencies are accurately captured. The newly developed high-frequency noise model is implemented in the complete surface-potential based MOSFET model HiSIM (Hiroshima-university STARC IGFET Model) for circuit simulation