Hideyuki Kikuchihara

HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits

The completely surface-potential-based MOSFET model HiSIM-HV for high-voltage applications of up to several hundred volts is reviewed, and recently developed new model capabilities are presented. HiSIM-HV enables a consistent evaluation of current and capacitance characteristics for symmetric and asymmetric high-voltage MOSFETs due to a consistent description of the potential distribution across the MOSFET channel as well as the resistive drift regions. The anomalous features, often observed in the capacitances, are explained by large potential drops in the drift regions. Accurate modeling of the overlap region between the gate and drift region is also demonstrated. Different device features based on different device structures are well explained by the geometrical differences.

Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices

High-voltage (HV) metal-oxide-semiconductor field-effect transistors (MOSFETs) of the laterally diffused metal-oxide-semiconductor (LDMOS) type enable applications over a wide range of bias voltages by optimizing the combined structure of MOSFET and drift region at its drain side. We report a physically accurate compact resistor model of the LDMOS drift region, adapted to the special requirements of the combined structure with a MOSFET. In particular, the reported resistor model captures the effects of the 2-D current flow in the drift region with its complicated bias dependence. The resistor model considers two device-structure-dependent potentials, namely, the internal node potential within the highly resistive drift region and the potential underneath the gate overlap region. The consistent potential-based description over the complete LDMOS device is the key modeling technology for enabling the accurate reproduction of the bias-dependent 2-D current flow and the resulting I-V characteristics for a wide range of structure variations with a small number of only six fitting parameters. The reported quasi-2-D resistor model is implemented in the second-generation Hiroshima-university STARC IGFET Model-High Voltage (HiSIM-HV) compact models for HV MOSFETs and is expected to be useful for both, optimization of LDMOS circuits and devices.

Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs

An investigation of the carrier trapping influence on device characteristics in poly-Si thin-film transistors (TFTs) is reported. Particular focus is laid on the transient characteristics, which is influenced by the carrier trapping during the device operation. On the basis of these features, a compact model for TFT-circuit simulation has been developed, which considers the dynamically changing time constant of the carrier trapping in the framework of a complete surface-potential description, thus enabling modeling the dynamically varying trapped carrier density. The compact model is verified against measured characteristics of repeated switching.

The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs

This paper reviews the industry-standard surface-potential-based compact model HiSIM_HV for high-voltage MOSFETs, as, e.g., the lateral double-diffused MOS transistor, and introduces important improvements implemented in the second-generation model versions (HiSIM_HV2), for which open source code has been released since October 2011. HiSIM_HV solves the Poisson equation consistently within the intrinsic MOSFET, i.e., the gate-drift overlap region and the drain-side part of the drift region. Excess carrier concentrations in the drift region are accurately considered together with the velocity saturation effect. These modeling concepts enable a scalable compact model formulation with only one internal node. Fulfillment of the current continuity between MOSFET and drift parts is required for determining the internal node potential. An important enhancement implemented in the HiSIM_HV2 models is a physically accurate compact drift region resistance model, which captures the effects of the structure-dependent 2-D current flows in overlap and drift regions with their complicated bias dependence. Furthermore, compact modeling of gate overlap capacitance, leakage currents due to, e.g., impact ionization, self-heating, noise, and symmetry properties (smooth derivatives at zero drain-source voltage) have been substantially improved.

HiSIM-HV: A compact model for simulation of high-voltage-MOSFET circuits

The high-voltage MOSFET model HiSIM-HV is based on the HiSIM (Hiroshima-university STARC IGFET Model) model for conventional bulk MOSFETs [1, 2] and features a consistent potential description across MOSFET channel and drift region. Symmetric and asymmetric device types are covered for up to several 100 V switching capability. Accurate scaling properties for channel and drift-region length as well as channel width are also provided.

Power-Loss Prediction of High-Voltage SiC- mosfet Circuits With Compact Model Including Carrier-Trap Influences

The paper aims at clarifying the carrier-trapping influence on the electrical characteristics of silicon carbide (SiC) power MOSFETs and its inclusion in the simulation of SiC power mosfet-based circuits. Special focus is given on the degradation of the switching characteristics due to carrier trapping at SiC/SiO2 interface defects. A compact SiC power mosfet model, considering the trap density in the framework of a complete surface-potential description, has been developed by for accurate circuit simulation including power-loss prediction. The carrier trapping is verified to cause a switching delay, which results in switching loss increase. To achieve low power loss, trap-density reduction is shown to be vital. The maximum allowable trap density, which does not affect switching power loss, is discussed.

HiSIM-SOI: Complete surface-potential-based model valid for all SOI-structure types

The compact SOI-MOSFET model HiSIM-SOI based on the complete surface-potential description is presented. The model considers all possible charges induced in the device for the formulation of the Poisson equation, which is solved iteratively. Thus HiSIM-SOI is valid for any structural variations from thick to extremely thin SOI or BOX layers. The dynamic depletion between the fully and partially depleted conditions is well reproduced. It is also demonstrated that the floating-body effect can be accurately captured by considering the accumulated charge in the SOI layer for the solution of the Poisson equation. HiSIM-SOI is verified to correctly reproduce 2D-device simulation results automatically for different SOI-structure types without any additional option setting.

Spatial Distribution Analysis of Self-Heating Effect in High-Voltage MOSFETs

We have analyzed the self-heating effect in high-voltage (HV) MOSFETs, and have found that the self-heating effect first becomes larger with increasing gate-source voltage Vgs due to the current-density increase. However, it then starts to get smaller again with further increased Vgs. The reason is the spatial energy dissipation accompanied with the carrier injection into the resistive drift region. The effect is modeled and implemented into the circuit simulation model HiSIM-HV for HV-MOSFETs, and verified for real applications. It is shown that the magnitude of the self-heating effect on the drain current of HV-MOSFETs is not so drastic as normally expected. However, the self-heating which occurs in the drift region cannot be ignored, and must be considered as a thermal source for the electro/thermal simulation.

Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers

The reported compact SOI-MOSFET model hiroshima university starc igfet model-silicon on thin buried oxide (HiSIM-SOTB) has been developed for devices with ultrathin silicon on insulator (SOI) and buried oxide (BOX) layers. The potential distribution determined by the Poisson equation is accurately solved with the Newton iteration method across the SOI layer and in the substrate on the backside of the BOX for source and drain side of the device. All charges including accumulation and inversion charges on both side of the BOX are explicitly considered in the Poisson equation. It is found that different from the double-gate MOSFET, the influence of the impurity concentration of the bulk substrate below the BOX must be also explicitly considered to capture all measured properties of the silicon on thin buried oxide (SOTB) MOSFET. A further modeling challenge of the thin SOI and BOX layers, which had to be overcome, is that charge neutrality is not independently preserved at the front-gate oxide or at BOX side, but only totally within the whole device. Additionally it is found that, due to the consistent potential- and charge-based model formulation, the developed HiSIM-SOTB model can reproduce not only TCAD and measured SOTB device data but is even capable to predict the effects of structural variations, including the limiting case of the double-gate MOSFET structure.

Modeling of 2D bias control in overlap region of high-voltage MOSFETs for accurate device/circuit performance prediction

High-voltage MOSFETs enable wide biasrange applications realized only by optimizing the device structure. We have developed the compact model HiSIM_HV 2.0.0, based on the potential distribution in the device, which is useful for both device and circuit optimizations. By considering two device-structure dependent potentials, the internal node potential within the high resistive drift region and the potential underneath the gate overlap region, the model can reproduce I–V characteristics for a wide range of structure variations without additional fitting parameters.